#ifndef __BCM2708A0__


#define CM_SMPSCTL                                               HW_REGISTER_RW( 0x7e1010b8 ) 
   #define CM_SMPSCTL_MASK                                       0x000000f3
   #define CM_SMPSCTL_WIDTH                                      8
   #define CM_SMPSCTL_RESET                                      0000000000
      #define CM_SMPSCTL_BUSY_BITS                               7:7
      #define CM_SMPSCTL_BUSY_SET                                0x00000080
      #define CM_SMPSCTL_BUSY_CLR                                0xffffff7f
      #define CM_SMPSCTL_BUSY_MSB                                7
      #define CM_SMPSCTL_BUSY_LSB                                7
      #define CM_SMPSCTL_GATE_BITS                               6:6
      #define CM_SMPSCTL_GATE_SET                                0x00000040
      #define CM_SMPSCTL_GATE_CLR                                0xffffffbf
      #define CM_SMPSCTL_GATE_MSB                                6
      #define CM_SMPSCTL_GATE_LSB                                6
      #define CM_SMPSCTL_KILL_BITS                               5:5
      #define CM_SMPSCTL_KILL_SET                                0x00000020
      #define CM_SMPSCTL_KILL_CLR                                0xffffffdf
      #define CM_SMPSCTL_KILL_MSB                                5
      #define CM_SMPSCTL_KILL_LSB                                5
      #define CM_SMPSCTL_ENAB_BITS                               4:4
      #define CM_SMPSCTL_ENAB_SET                                0x00000010
      #define CM_SMPSCTL_ENAB_CLR                                0xffffffef
      #define CM_SMPSCTL_ENAB_MSB                                4
      #define CM_SMPSCTL_ENAB_LSB                                4
      #define CM_SMPSCTL_SRC_BITS                                1:0
      #define CM_SMPSCTL_SRC_SET                                 0x00000003
      #define CM_SMPSCTL_SRC_CLR                                 0xfffffffc
      #define CM_SMPSCTL_SRC_MSB                                 1
      #define CM_SMPSCTL_SRC_LSB                                 0
#define CM_SMPSDIV                                               HW_REGISTER_RW( 0x7e1010bc ) 
   #define CM_SMPSDIV_MASK                                       0x00007000
   #define CM_SMPSDIV_WIDTH                                      15
   #define CM_SMPSDIV_RESET                                      0000000000
      #define CM_SMPSDIV_DIV_BITS                                14:12
      #define CM_SMPSDIV_DIV_SET                                 0x00007000
      #define CM_SMPSDIV_DIV_CLR                                 0xffff8fff
      #define CM_SMPSDIV_DIV_MSB                                 14
      #define CM_SMPSDIV_DIV_LSB                                 12


// This file was generated by the create_regs script
#define CM_PASSWORD                                              0x5a000000
#define CM_BASE                                                  0x7e101000
#define CM_APB_ID                                                0x0000636d
#define CM_GNRICCTL                                              HW_REGISTER_RW( 0x7e101000 ) 
   #define CM_GNRICCTL_MASK                                      0x000fffff
   #define CM_GNRICCTL_WIDTH                                     20
   #define CM_GNRICCTL_RESET                                     0000000000
      #define CM_GNRICCTL_FLIP_BITS                              11:11
      #define CM_GNRICCTL_FLIP_SET                               0x00000800
      #define CM_GNRICCTL_FLIP_CLR                               0xfffff7ff
      #define CM_GNRICCTL_FLIP_MSB                               11
      #define CM_GNRICCTL_FLIP_LSB                               11
      #define CM_GNRICCTL_MASH_BITS                              10:9
      #define CM_GNRICCTL_MASH_SET                               0x00000600
      #define CM_GNRICCTL_MASH_CLR                               0xfffff9ff
      #define CM_GNRICCTL_MASH_MSB                               10
      #define CM_GNRICCTL_MASH_LSB                               9
      #define CM_GNRICCTL_BUSYD_BITS                             8:8
      #define CM_GNRICCTL_BUSYD_SET                              0x00000100
      #define CM_GNRICCTL_BUSYD_CLR                              0xfffffeff
      #define CM_GNRICCTL_BUSYD_MSB                              8
      #define CM_GNRICCTL_BUSYD_LSB                              8
      #define CM_GNRICCTL_BUSY_BITS                              7:7
      #define CM_GNRICCTL_BUSY_SET                               0x00000080
      #define CM_GNRICCTL_BUSY_CLR                               0xffffff7f
      #define CM_GNRICCTL_BUSY_MSB                               7
      #define CM_GNRICCTL_BUSY_LSB                               7
      #define CM_GNRICCTL_GATE_BITS                              6:6
      #define CM_GNRICCTL_GATE_SET                               0x00000040
      #define CM_GNRICCTL_GATE_CLR                               0xffffffbf
      #define CM_GNRICCTL_GATE_MSB                               6
      #define CM_GNRICCTL_GATE_LSB                               6
      #define CM_GNRICCTL_KILL_BITS                              5:5
      #define CM_GNRICCTL_KILL_SET                               0x00000020
      #define CM_GNRICCTL_KILL_CLR                               0xffffffdf
      #define CM_GNRICCTL_KILL_MSB                               5
      #define CM_GNRICCTL_KILL_LSB                               5
      #define CM_GNRICCTL_ENAB_BITS                              4:4
      #define CM_GNRICCTL_ENAB_SET                               0x00000010
      #define CM_GNRICCTL_ENAB_CLR                               0xffffffef
      #define CM_GNRICCTL_ENAB_MSB                               4
      #define CM_GNRICCTL_ENAB_LSB                               4
      #define CM_GNRICCTL_SRC_BITS                               3:0
      #define CM_GNRICCTL_SRC_SET                                0x0000000f
      #define CM_GNRICCTL_SRC_CLR                                0xfffffff0
      #define CM_GNRICCTL_SRC_MSB                                3
      #define CM_GNRICCTL_SRC_LSB                                0
#define CM_GNRICDIV                                              HW_REGISTER_RW( 0x7e101004 ) 
   #define CM_GNRICDIV_MASK                                      0x00ffffff
   #define CM_GNRICDIV_WIDTH                                     24
   #define CM_GNRICDIV_RESET                                     0000000000
      #define CM_GNRICDIV_DIV_BITS                               23:0
      #define CM_GNRICDIV_DIV_SET                                0x00ffffff
      #define CM_GNRICDIV_DIV_CLR                                0xff000000
      #define CM_GNRICDIV_DIV_MSB                                23
      #define CM_GNRICDIV_DIV_LSB                                0
#define CM_VPUCTL                                                HW_REGISTER_RW( 0x7e101008 ) 
   #define CM_VPUCTL_MASK                                        0x000003cf
   #define CM_VPUCTL_WIDTH                                       10
   #define CM_VPUCTL_RESET                                       0x00000041
      #define CM_VPUCTL_FRAC_BITS                                9:9
      #define CM_VPUCTL_FRAC_SET                                 0x00000200
      #define CM_VPUCTL_FRAC_CLR                                 0xfffffdff
      #define CM_VPUCTL_FRAC_MSB                                 9
      #define CM_VPUCTL_FRAC_LSB                                 9
      #define CM_VPUCTL_BUSYD_BITS                               8:8
      #define CM_VPUCTL_BUSYD_SET                                0x00000100
      #define CM_VPUCTL_BUSYD_CLR                                0xfffffeff
      #define CM_VPUCTL_BUSYD_MSB                                8
      #define CM_VPUCTL_BUSYD_LSB                                8
      #define CM_VPUCTL_BUSY_BITS                                7:7
      #define CM_VPUCTL_BUSY_SET                                 0x00000080
      #define CM_VPUCTL_BUSY_CLR                                 0xffffff7f
      #define CM_VPUCTL_BUSY_MSB                                 7
      #define CM_VPUCTL_BUSY_LSB                                 7
      #define CM_VPUCTL_GATE_BITS                                6:6
      #define CM_VPUCTL_GATE_SET                                 0x00000040
      #define CM_VPUCTL_GATE_CLR                                 0xffffffbf
      #define CM_VPUCTL_GATE_MSB                                 6
      #define CM_VPUCTL_GATE_LSB                                 6
      #define CM_VPUCTL_SRC_BITS                                 3:0
      #define CM_VPUCTL_SRC_SET                                  0x0000000f
      #define CM_VPUCTL_SRC_CLR                                  0xfffffff0
      #define CM_VPUCTL_SRC_MSB                                  3
      #define CM_VPUCTL_SRC_LSB                                  0
#define CM_VPUDIV                                                HW_REGISTER_RW( 0x7e10100c ) 
   #define CM_VPUDIV_MASK                                        0x00fffff0
   #define CM_VPUDIV_WIDTH                                       24
   #define CM_VPUDIV_RESET                                       0x00001000
      #define CM_VPUDIV_DIV_BITS                                 23:4
      #define CM_VPUDIV_DIV_SET                                  0x00fffff0
      #define CM_VPUDIV_DIV_CLR                                  0xff00000f
      #define CM_VPUDIV_DIV_MSB                                  23
      #define CM_VPUDIV_DIV_LSB                                  4
#define CM_SYSCTL                                                HW_REGISTER_RW( 0x7e101010 ) 
   #define CM_SYSCTL_MASK                                        0x00000040
   #define CM_SYSCTL_WIDTH                                       7
   #define CM_SYSCTL_RESET                                       0x00000040
      #define CM_SYSCTL_GATE_BITS                                6:6
      #define CM_SYSCTL_GATE_SET                                 0x00000040
      #define CM_SYSCTL_GATE_CLR                                 0xffffffbf
      #define CM_SYSCTL_GATE_MSB                                 6
      #define CM_SYSCTL_GATE_LSB                                 6
#define CM_SYSDIV                                                HW_REGISTER_RO( 0x7e101014 ) 
   #define CM_SYSDIV_MASK                                        0x00001000
   #define CM_SYSDIV_WIDTH                                       13
   #define CM_SYSDIV_RESET                                       0x00001000
      #define CM_SYSDIV_DIV_BITS                                 12:12
      #define CM_SYSDIV_DIV_SET                                  0x00001000
      #define CM_SYSDIV_DIV_CLR                                  0xffffefff
      #define CM_SYSDIV_DIV_MSB                                  12
      #define CM_SYSDIV_DIV_LSB                                  12
#define CM_PERIACTL                                              HW_REGISTER_RW( 0x7e101018 ) 
   #define CM_PERIACTL_MASK                                      0x00000040
   #define CM_PERIACTL_WIDTH                                     7
   #define CM_PERIACTL_RESET                                     0x00000040
      #define CM_PERIACTL_GATE_BITS                              6:6
      #define CM_PERIACTL_GATE_SET                               0x00000040
      #define CM_PERIACTL_GATE_CLR                               0xffffffbf
      #define CM_PERIACTL_GATE_MSB                               6
      #define CM_PERIACTL_GATE_LSB                               6
#define CM_PERIADIV                                              HW_REGISTER_RO( 0x7e10101c ) 
   #define CM_PERIADIV_MASK                                      0x00001000
   #define CM_PERIADIV_WIDTH                                     13
   #define CM_PERIADIV_RESET                                     0x00001000
      #define CM_PERIADIV_DIV_BITS                               12:12
      #define CM_PERIADIV_DIV_SET                                0x00001000
      #define CM_PERIADIV_DIV_CLR                                0xffffefff
      #define CM_PERIADIV_DIV_MSB                                12
      #define CM_PERIADIV_DIV_LSB                                12
#define CM_PERIICTL                                              HW_REGISTER_RW( 0x7e101020 ) 
   #define CM_PERIICTL_MASK                                      0x00000040
   #define CM_PERIICTL_WIDTH                                     7
   #define CM_PERIICTL_RESET                                     0000000000
      #define CM_PERIICTL_GATE_BITS                              6:6
      #define CM_PERIICTL_GATE_SET                               0x00000040
      #define CM_PERIICTL_GATE_CLR                               0xffffffbf
      #define CM_PERIICTL_GATE_MSB                               6
      #define CM_PERIICTL_GATE_LSB                               6
#define CM_PERIIDIV                                              HW_REGISTER_RO( 0x7e101024 ) 
   #define CM_PERIIDIV_MASK                                      0x00001000
   #define CM_PERIIDIV_WIDTH                                     13
   #define CM_PERIIDIV_RESET                                     0x00001000
      #define CM_PERIIDIV_DIV_BITS                               12:12
      #define CM_PERIIDIV_DIV_SET                                0x00001000
      #define CM_PERIIDIV_DIV_CLR                                0xffffefff
      #define CM_PERIIDIV_DIV_MSB                                12
      #define CM_PERIIDIV_DIV_LSB                                12
#define CM_H264CTL                                               HW_REGISTER_RW( 0x7e101028 ) 
   #define CM_H264CTL_MASK                                       0x000003ff
   #define CM_H264CTL_WIDTH                                      10
   #define CM_H264CTL_RESET                                      0x00000040
      #define CM_H264CTL_FRAC_BITS                               9:9
      #define CM_H264CTL_FRAC_SET                                0x00000200
      #define CM_H264CTL_FRAC_CLR                                0xfffffdff
      #define CM_H264CTL_FRAC_MSB                                9
      #define CM_H264CTL_FRAC_LSB                                9
      #define CM_H264CTL_BUSYD_BITS                              8:8
      #define CM_H264CTL_BUSYD_SET                               0x00000100
      #define CM_H264CTL_BUSYD_CLR                               0xfffffeff
      #define CM_H264CTL_BUSYD_MSB                               8
      #define CM_H264CTL_BUSYD_LSB                               8
      #define CM_H264CTL_BUSY_BITS                               7:7
      #define CM_H264CTL_BUSY_SET                                0x00000080
      #define CM_H264CTL_BUSY_CLR                                0xffffff7f
      #define CM_H264CTL_BUSY_MSB                                7
      #define CM_H264CTL_BUSY_LSB                                7
      #define CM_H264CTL_GATE_BITS                               6:6
      #define CM_H264CTL_GATE_SET                                0x00000040
      #define CM_H264CTL_GATE_CLR                                0xffffffbf
      #define CM_H264CTL_GATE_MSB                                6
      #define CM_H264CTL_GATE_LSB                                6
      #define CM_H264CTL_KILL_BITS                               5:5
      #define CM_H264CTL_KILL_SET                                0x00000020
      #define CM_H264CTL_KILL_CLR                                0xffffffdf
      #define CM_H264CTL_KILL_MSB                                5
      #define CM_H264CTL_KILL_LSB                                5
      #define CM_H264CTL_ENAB_BITS                               4:4
      #define CM_H264CTL_ENAB_SET                                0x00000010
      #define CM_H264CTL_ENAB_CLR                                0xffffffef
      #define CM_H264CTL_ENAB_MSB                                4
      #define CM_H264CTL_ENAB_LSB                                4
      #define CM_H264CTL_SRC_BITS                                3:0
      #define CM_H264CTL_SRC_SET                                 0x0000000f
      #define CM_H264CTL_SRC_CLR                                 0xfffffff0
      #define CM_H264CTL_SRC_MSB                                 3
      #define CM_H264CTL_SRC_LSB                                 0
#define CM_H264DIV                                               HW_REGISTER_RW( 0x7e10102c ) 
   #define CM_H264DIV_MASK                                       0x0000fff0
   #define CM_H264DIV_WIDTH                                      16
   #define CM_H264DIV_RESET                                      0000000000
      #define CM_H264DIV_DIV_BITS                                15:4
      #define CM_H264DIV_DIV_SET                                 0x0000fff0
      #define CM_H264DIV_DIV_CLR                                 0xffff000f
      #define CM_H264DIV_DIV_MSB                                 15
      #define CM_H264DIV_DIV_LSB                                 4
#define CM_ISPCTL                                                HW_REGISTER_RW( 0x7e101030 ) 
   #define CM_ISPCTL_MASK                                        0x000003ff
   #define CM_ISPCTL_WIDTH                                       10
   #define CM_ISPCTL_RESET                                       0x00000040
      #define CM_ISPCTL_FRAC_BITS                                9:9
      #define CM_ISPCTL_FRAC_SET                                 0x00000200
      #define CM_ISPCTL_FRAC_CLR                                 0xfffffdff
      #define CM_ISPCTL_FRAC_MSB                                 9
      #define CM_ISPCTL_FRAC_LSB                                 9
      #define CM_ISPCTL_BUSYD_BITS                               8:8
      #define CM_ISPCTL_BUSYD_SET                                0x00000100
      #define CM_ISPCTL_BUSYD_CLR                                0xfffffeff
      #define CM_ISPCTL_BUSYD_MSB                                8
      #define CM_ISPCTL_BUSYD_LSB                                8
      #define CM_ISPCTL_BUSY_BITS                                7:7
      #define CM_ISPCTL_BUSY_SET                                 0x00000080
      #define CM_ISPCTL_BUSY_CLR                                 0xffffff7f
      #define CM_ISPCTL_BUSY_MSB                                 7
      #define CM_ISPCTL_BUSY_LSB                                 7
      #define CM_ISPCTL_GATE_BITS                                6:6
      #define CM_ISPCTL_GATE_SET                                 0x00000040
      #define CM_ISPCTL_GATE_CLR                                 0xffffffbf
      #define CM_ISPCTL_GATE_MSB                                 6
      #define CM_ISPCTL_GATE_LSB                                 6
      #define CM_ISPCTL_KILL_BITS                                5:5
      #define CM_ISPCTL_KILL_SET                                 0x00000020
      #define CM_ISPCTL_KILL_CLR                                 0xffffffdf
      #define CM_ISPCTL_KILL_MSB                                 5
      #define CM_ISPCTL_KILL_LSB                                 5
      #define CM_ISPCTL_ENAB_BITS                                4:4
      #define CM_ISPCTL_ENAB_SET                                 0x00000010
      #define CM_ISPCTL_ENAB_CLR                                 0xffffffef
      #define CM_ISPCTL_ENAB_MSB                                 4
      #define CM_ISPCTL_ENAB_LSB                                 4
      #define CM_ISPCTL_SRC_BITS                                 3:0
      #define CM_ISPCTL_SRC_SET                                  0x0000000f
      #define CM_ISPCTL_SRC_CLR                                  0xfffffff0
      #define CM_ISPCTL_SRC_MSB                                  3
      #define CM_ISPCTL_SRC_LSB                                  0
#define CM_ISPDIV                                                HW_REGISTER_RW( 0x7e101034 ) 
   #define CM_ISPDIV_MASK                                        0x0000fff0
   #define CM_ISPDIV_WIDTH                                       16
   #define CM_ISPDIV_RESET                                       0000000000
      #define CM_ISPDIV_DIV_BITS                                 15:4
      #define CM_ISPDIV_DIV_SET                                  0x0000fff0
      #define CM_ISPDIV_DIV_CLR                                  0xffff000f
      #define CM_ISPDIV_DIV_MSB                                  15
      #define CM_ISPDIV_DIV_LSB                                  4
#define CM_ARMCTL                                                HW_REGISTER_RW( 0x7e1011b0 ) 
   #define CM_ARMCTL_MASK                                        0x000013bf
   #define CM_ARMCTL_WIDTH                                       13
   #define CM_ARMCTL_RESET                                       0x00000004
      #define CM_ARMCTL_AXIHALF_BITS                             12:12
      #define CM_ARMCTL_AXIHALF_SET                              0x00001000
      #define CM_ARMCTL_AXIHALF_CLR                              0xffffefff
      #define CM_ARMCTL_AXIHALF_MSB                              12
      #define CM_ARMCTL_AXIHALF_LSB                              12
      #define CM_ARMCTL_FRAC_BITS                                9:9
      #define CM_ARMCTL_FRAC_SET                                 0x00000200
      #define CM_ARMCTL_FRAC_CLR                                 0xfffffdff
      #define CM_ARMCTL_FRAC_MSB                                 9
      #define CM_ARMCTL_FRAC_LSB                                 9
      #define CM_ARMCTL_BUSYD_BITS                               8:8
      #define CM_ARMCTL_BUSYD_SET                                0x00000100
      #define CM_ARMCTL_BUSYD_CLR                                0xfffffeff
      #define CM_ARMCTL_BUSYD_MSB                                8
      #define CM_ARMCTL_BUSYD_LSB                                8
      #define CM_ARMCTL_BUSY_BITS                                7:7
      #define CM_ARMCTL_BUSY_SET                                 0x00000080
      #define CM_ARMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_ARMCTL_BUSY_MSB                                 7
      #define CM_ARMCTL_BUSY_LSB                                 7
      #define CM_ARMCTL_KILL_BITS                                5:5
      #define CM_ARMCTL_KILL_SET                                 0x00000020
      #define CM_ARMCTL_KILL_CLR                                 0xffffffdf
      #define CM_ARMCTL_KILL_MSB                                 5
      #define CM_ARMCTL_KILL_LSB                                 5
      #define CM_ARMCTL_ENAB_BITS                                4:4
      #define CM_ARMCTL_ENAB_SET                                 0x00000010
      #define CM_ARMCTL_ENAB_CLR                                 0xffffffef
      #define CM_ARMCTL_ENAB_MSB                                 4
      #define CM_ARMCTL_ENAB_LSB                                 4
      #define CM_ARMCTL_SRC_BITS                                 3:0
      #define CM_ARMCTL_SRC_SET                                  0x0000000f
      #define CM_ARMCTL_SRC_CLR                                  0xfffffff0
      #define CM_ARMCTL_SRC_MSB                                  3
      #define CM_ARMCTL_SRC_LSB                                  0
#define CM_ARMDIV                                                HW_REGISTER_RO( 0x7e1011b4 ) 
   #define CM_ARMDIV_MASK                                        0x00001000
   #define CM_ARMDIV_WIDTH                                       13
   #define CM_ARMDIV_RESET                                       0x00001000
      #define CM_ARMDIV_DIV_BITS                                 12:12
      #define CM_ARMDIV_DIV_SET                                  0x00001000
      #define CM_ARMDIV_DIV_CLR                                  0xffffefff
      #define CM_ARMDIV_DIV_MSB                                  12
      #define CM_ARMDIV_DIV_LSB                                  12
#define CM_SDCCTL                                                HW_REGISTER_RW( 0x7e1011a8 ) 
   #define CM_SDCCTL_MASK                                        0x0003f3bf
   #define CM_SDCCTL_WIDTH                                       18
   #define CM_SDCCTL_RESET                                       0x00004000
      #define CM_SDCCTL_UPDATE_BITS                              17:17
      #define CM_SDCCTL_UPDATE_SET                               0x00020000
      #define CM_SDCCTL_UPDATE_CLR                               0xfffdffff
      #define CM_SDCCTL_UPDATE_MSB                               17
      #define CM_SDCCTL_UPDATE_LSB                               17
      #define CM_SDCCTL_ACCPT_BITS                               16:16
      #define CM_SDCCTL_ACCPT_SET                                0x00010000
      #define CM_SDCCTL_ACCPT_CLR                                0xfffeffff
      #define CM_SDCCTL_ACCPT_MSB                                16
      #define CM_SDCCTL_ACCPT_LSB                                16
      #define CM_SDCCTL_CTRL_BITS                                15:12
      #define CM_SDCCTL_CTRL_SET                                 0x0000f000
      #define CM_SDCCTL_CTRL_CLR                                 0xffff0fff
      #define CM_SDCCTL_CTRL_MSB                                 15
      #define CM_SDCCTL_CTRL_LSB                                 12
      #define CM_SDCCTL_FRAC_BITS                                9:9
      #define CM_SDCCTL_FRAC_SET                                 0x00000200
      #define CM_SDCCTL_FRAC_CLR                                 0xfffffdff
      #define CM_SDCCTL_FRAC_MSB                                 9
      #define CM_SDCCTL_FRAC_LSB                                 9
      #define CM_SDCCTL_BUSYD_BITS                               8:8
      #define CM_SDCCTL_BUSYD_SET                                0x00000100
      #define CM_SDCCTL_BUSYD_CLR                                0xfffffeff
      #define CM_SDCCTL_BUSYD_MSB                                8
      #define CM_SDCCTL_BUSYD_LSB                                8
      #define CM_SDCCTL_BUSY_BITS                                7:7
      #define CM_SDCCTL_BUSY_SET                                 0x00000080
      #define CM_SDCCTL_BUSY_CLR                                 0xffffff7f
      #define CM_SDCCTL_BUSY_MSB                                 7
      #define CM_SDCCTL_BUSY_LSB                                 7
      #define CM_SDCCTL_KILL_BITS                                5:5
      #define CM_SDCCTL_KILL_SET                                 0x00000020
      #define CM_SDCCTL_KILL_CLR                                 0xffffffdf
      #define CM_SDCCTL_KILL_MSB                                 5
      #define CM_SDCCTL_KILL_LSB                                 5
      #define CM_SDCCTL_ENAB_BITS                                4:4
      #define CM_SDCCTL_ENAB_SET                                 0x00000010
      #define CM_SDCCTL_ENAB_CLR                                 0xffffffef
      #define CM_SDCCTL_ENAB_MSB                                 4
      #define CM_SDCCTL_ENAB_LSB                                 4
      #define CM_SDCCTL_SRC_BITS                                 3:0
      #define CM_SDCCTL_SRC_SET                                  0x0000000f
      #define CM_SDCCTL_SRC_CLR                                  0xfffffff0
      #define CM_SDCCTL_SRC_MSB                                  3
      #define CM_SDCCTL_SRC_LSB                                  0
#define CM_SDCDIV                                                HW_REGISTER_RW( 0x7e1011ac ) 
   #define CM_SDCDIV_MASK                                        0x0003f000
   #define CM_SDCDIV_WIDTH                                       18
   #define CM_SDCDIV_RESET                                       0000000000
      #define CM_SDCDIV_DIV_BITS                                 17:12
      #define CM_SDCDIV_DIV_SET                                  0x0003f000
      #define CM_SDCDIV_DIV_CLR                                  0xfffc0fff
      #define CM_SDCDIV_DIV_MSB                                  17
      #define CM_SDCDIV_DIV_LSB                                  12
#define CM_V3DCTL                                                HW_REGISTER_RW( 0x7e101038 ) 
   #define CM_V3DCTL_MASK                                        0x000003ff
   #define CM_V3DCTL_WIDTH                                       10
   #define CM_V3DCTL_RESET                                       0x00000040
      #define CM_V3DCTL_FRAC_BITS                                9:9
      #define CM_V3DCTL_FRAC_SET                                 0x00000200
      #define CM_V3DCTL_FRAC_CLR                                 0xfffffdff
      #define CM_V3DCTL_FRAC_MSB                                 9
      #define CM_V3DCTL_FRAC_LSB                                 9
      #define CM_V3DCTL_BUSYD_BITS                               8:8
      #define CM_V3DCTL_BUSYD_SET                                0x00000100
      #define CM_V3DCTL_BUSYD_CLR                                0xfffffeff
      #define CM_V3DCTL_BUSYD_MSB                                8
      #define CM_V3DCTL_BUSYD_LSB                                8
      #define CM_V3DCTL_BUSY_BITS                                7:7
      #define CM_V3DCTL_BUSY_SET                                 0x00000080
      #define CM_V3DCTL_BUSY_CLR                                 0xffffff7f
      #define CM_V3DCTL_BUSY_MSB                                 7
      #define CM_V3DCTL_BUSY_LSB                                 7
      #define CM_V3DCTL_GATE_BITS                                6:6
      #define CM_V3DCTL_GATE_SET                                 0x00000040
      #define CM_V3DCTL_GATE_CLR                                 0xffffffbf
      #define CM_V3DCTL_GATE_MSB                                 6
      #define CM_V3DCTL_GATE_LSB                                 6
      #define CM_V3DCTL_KILL_BITS                                5:5
      #define CM_V3DCTL_KILL_SET                                 0x00000020
      #define CM_V3DCTL_KILL_CLR                                 0xffffffdf
      #define CM_V3DCTL_KILL_MSB                                 5
      #define CM_V3DCTL_KILL_LSB                                 5
      #define CM_V3DCTL_ENAB_BITS                                4:4
      #define CM_V3DCTL_ENAB_SET                                 0x00000010
      #define CM_V3DCTL_ENAB_CLR                                 0xffffffef
      #define CM_V3DCTL_ENAB_MSB                                 4
      #define CM_V3DCTL_ENAB_LSB                                 4
      #define CM_V3DCTL_SRC_BITS                                 3:0
      #define CM_V3DCTL_SRC_SET                                  0x0000000f
      #define CM_V3DCTL_SRC_CLR                                  0xfffffff0
      #define CM_V3DCTL_SRC_MSB                                  3
      #define CM_V3DCTL_SRC_LSB                                  0
#define CM_V3DDIV                                                HW_REGISTER_RW( 0x7e10103c ) 
   #define CM_V3DDIV_MASK                                        0x0000fff0
   #define CM_V3DDIV_WIDTH                                       16
   #define CM_V3DDIV_RESET                                       0000000000
      #define CM_V3DDIV_DIV_BITS                                 15:4
      #define CM_V3DDIV_DIV_SET                                  0x0000fff0
      #define CM_V3DDIV_DIV_CLR                                  0xffff000f
      #define CM_V3DDIV_DIV_MSB                                  15
      #define CM_V3DDIV_DIV_LSB                                  4
#define CM_CAM0CTL                                               HW_REGISTER_RW( 0x7e101040 ) 
   #define CM_CAM0CTL_MASK                                       0x000003bf
   #define CM_CAM0CTL_WIDTH                                      10
   #define CM_CAM0CTL_RESET                                      0000000000
      #define CM_CAM0CTL_FRAC_BITS                               9:9
      #define CM_CAM0CTL_FRAC_SET                                0x00000200
      #define CM_CAM0CTL_FRAC_CLR                                0xfffffdff
      #define CM_CAM0CTL_FRAC_MSB                                9
      #define CM_CAM0CTL_FRAC_LSB                                9
      #define CM_CAM0CTL_BUSYD_BITS                              8:8
      #define CM_CAM0CTL_BUSYD_SET                               0x00000100
      #define CM_CAM0CTL_BUSYD_CLR                               0xfffffeff
      #define CM_CAM0CTL_BUSYD_MSB                               8
      #define CM_CAM0CTL_BUSYD_LSB                               8
      #define CM_CAM0CTL_BUSY_BITS                               7:7
      #define CM_CAM0CTL_BUSY_SET                                0x00000080
      #define CM_CAM0CTL_BUSY_CLR                                0xffffff7f
      #define CM_CAM0CTL_BUSY_MSB                                7
      #define CM_CAM0CTL_BUSY_LSB                                7
      #define CM_CAM0CTL_KILL_BITS                               5:5
      #define CM_CAM0CTL_KILL_SET                                0x00000020
      #define CM_CAM0CTL_KILL_CLR                                0xffffffdf
      #define CM_CAM0CTL_KILL_MSB                                5
      #define CM_CAM0CTL_KILL_LSB                                5
      #define CM_CAM0CTL_ENAB_BITS                               4:4
      #define CM_CAM0CTL_ENAB_SET                                0x00000010
      #define CM_CAM0CTL_ENAB_CLR                                0xffffffef
      #define CM_CAM0CTL_ENAB_MSB                                4
      #define CM_CAM0CTL_ENAB_LSB                                4
      #define CM_CAM0CTL_SRC_BITS                                3:0
      #define CM_CAM0CTL_SRC_SET                                 0x0000000f
      #define CM_CAM0CTL_SRC_CLR                                 0xfffffff0
      #define CM_CAM0CTL_SRC_MSB                                 3
      #define CM_CAM0CTL_SRC_LSB                                 0
#define CM_CAM0DIV                                               HW_REGISTER_RW( 0x7e101044 ) 
   #define CM_CAM0DIV_MASK                                       0x0000fff0
   #define CM_CAM0DIV_WIDTH                                      16
   #define CM_CAM0DIV_RESET                                      0000000000
      #define CM_CAM0DIV_DIV_BITS                                15:4
      #define CM_CAM0DIV_DIV_SET                                 0x0000fff0
      #define CM_CAM0DIV_DIV_CLR                                 0xffff000f
      #define CM_CAM0DIV_DIV_MSB                                 15
      #define CM_CAM0DIV_DIV_LSB                                 4
#define CM_CAM1CTL                                               HW_REGISTER_RW( 0x7e101048 ) 
   #define CM_CAM1CTL_MASK                                       0x000003bf
   #define CM_CAM1CTL_WIDTH                                      10
   #define CM_CAM1CTL_RESET                                      0000000000
      #define CM_CAM1CTL_FRAC_BITS                               9:9
      #define CM_CAM1CTL_FRAC_SET                                0x00000200
      #define CM_CAM1CTL_FRAC_CLR                                0xfffffdff
      #define CM_CAM1CTL_FRAC_MSB                                9
      #define CM_CAM1CTL_FRAC_LSB                                9
      #define CM_CAM1CTL_BUSYD_BITS                              8:8
      #define CM_CAM1CTL_BUSYD_SET                               0x00000100
      #define CM_CAM1CTL_BUSYD_CLR                               0xfffffeff
      #define CM_CAM1CTL_BUSYD_MSB                               8
      #define CM_CAM1CTL_BUSYD_LSB                               8
      #define CM_CAM1CTL_BUSY_BITS                               7:7
      #define CM_CAM1CTL_BUSY_SET                                0x00000080
      #define CM_CAM1CTL_BUSY_CLR                                0xffffff7f
      #define CM_CAM1CTL_BUSY_MSB                                7
      #define CM_CAM1CTL_BUSY_LSB                                7
      #define CM_CAM1CTL_KILL_BITS                               5:5
      #define CM_CAM1CTL_KILL_SET                                0x00000020
      #define CM_CAM1CTL_KILL_CLR                                0xffffffdf
      #define CM_CAM1CTL_KILL_MSB                                5
      #define CM_CAM1CTL_KILL_LSB                                5
      #define CM_CAM1CTL_ENAB_BITS                               4:4
      #define CM_CAM1CTL_ENAB_SET                                0x00000010
      #define CM_CAM1CTL_ENAB_CLR                                0xffffffef
      #define CM_CAM1CTL_ENAB_MSB                                4
      #define CM_CAM1CTL_ENAB_LSB                                4
      #define CM_CAM1CTL_SRC_BITS                                3:0
      #define CM_CAM1CTL_SRC_SET                                 0x0000000f
      #define CM_CAM1CTL_SRC_CLR                                 0xfffffff0
      #define CM_CAM1CTL_SRC_MSB                                 3
      #define CM_CAM1CTL_SRC_LSB                                 0
#define CM_CAM1DIV                                               HW_REGISTER_RW( 0x7e10104c ) 
   #define CM_CAM1DIV_MASK                                       0x0000fff0
   #define CM_CAM1DIV_WIDTH                                      16
   #define CM_CAM1DIV_RESET                                      0000000000
      #define CM_CAM1DIV_DIV_BITS                                15:4
      #define CM_CAM1DIV_DIV_SET                                 0x0000fff0
      #define CM_CAM1DIV_DIV_CLR                                 0xffff000f
      #define CM_CAM1DIV_DIV_MSB                                 15
      #define CM_CAM1DIV_DIV_LSB                                 4
#define CM_CCP2CTL                                               HW_REGISTER_RW( 0x7e101050 ) 
   #define CM_CCP2CTL_MASK                                       0x00000397
   #define CM_CCP2CTL_WIDTH                                      10
   #define CM_CCP2CTL_RESET                                      0000000000
      #define CM_CCP2CTL_FRAC_BITS                               9:9
      #define CM_CCP2CTL_FRAC_SET                                0x00000200
      #define CM_CCP2CTL_FRAC_CLR                                0xfffffdff
      #define CM_CCP2CTL_FRAC_MSB                                9
      #define CM_CCP2CTL_FRAC_LSB                                9
      #define CM_CCP2CTL_BUSYD_BITS                              8:8
      #define CM_CCP2CTL_BUSYD_SET                               0x00000100
      #define CM_CCP2CTL_BUSYD_CLR                               0xfffffeff
      #define CM_CCP2CTL_BUSYD_MSB                               8
      #define CM_CCP2CTL_BUSYD_LSB                               8
      #define CM_CCP2CTL_BUSY_BITS                               7:7
      #define CM_CCP2CTL_BUSY_SET                                0x00000080
      #define CM_CCP2CTL_BUSY_CLR                                0xffffff7f
      #define CM_CCP2CTL_BUSY_MSB                                7
      #define CM_CCP2CTL_BUSY_LSB                                7
      #define CM_CCP2CTL_ENAB_BITS                               4:4
      #define CM_CCP2CTL_ENAB_SET                                0x00000010
      #define CM_CCP2CTL_ENAB_CLR                                0xffffffef
      #define CM_CCP2CTL_ENAB_MSB                                4
      #define CM_CCP2CTL_ENAB_LSB                                4
      #define CM_CCP2CTL_SRC_BITS                                2:0
      #define CM_CCP2CTL_SRC_SET                                 0x00000007
      #define CM_CCP2CTL_SRC_CLR                                 0xfffffff8
      #define CM_CCP2CTL_SRC_MSB                                 2
      #define CM_CCP2CTL_SRC_LSB                                 0
#define CM_CCP2DIV                                               HW_REGISTER_RO( 0x7e101054 ) 
   #define CM_CCP2DIV_MASK                                       0x00001000
   #define CM_CCP2DIV_WIDTH                                      13
   #define CM_CCP2DIV_RESET                                      0x00001000
      #define CM_CCP2DIV_DIV_BITS                                12:12
      #define CM_CCP2DIV_DIV_SET                                 0x00001000
      #define CM_CCP2DIV_DIV_CLR                                 0xffffefff
      #define CM_CCP2DIV_DIV_MSB                                 12
      #define CM_CCP2DIV_DIV_LSB                                 12
#define CM_DSI0ECTL                                              HW_REGISTER_RW( 0x7e101058 ) 
   #define CM_DSI0ECTL_MASK                                      0x000003bf
   #define CM_DSI0ECTL_WIDTH                                     10
   #define CM_DSI0ECTL_RESET                                     0000000000
      #define CM_DSI0ECTL_FRAC_BITS                              9:9
      #define CM_DSI0ECTL_FRAC_SET                               0x00000200
      #define CM_DSI0ECTL_FRAC_CLR                               0xfffffdff
      #define CM_DSI0ECTL_FRAC_MSB                               9
      #define CM_DSI0ECTL_FRAC_LSB                               9
      #define CM_DSI0ECTL_BUSYD_BITS                             8:8
      #define CM_DSI0ECTL_BUSYD_SET                              0x00000100
      #define CM_DSI0ECTL_BUSYD_CLR                              0xfffffeff
      #define CM_DSI0ECTL_BUSYD_MSB                              8
      #define CM_DSI0ECTL_BUSYD_LSB                              8
      #define CM_DSI0ECTL_BUSY_BITS                              7:7
      #define CM_DSI0ECTL_BUSY_SET                               0x00000080
      #define CM_DSI0ECTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI0ECTL_BUSY_MSB                               7
      #define CM_DSI0ECTL_BUSY_LSB                               7
      #define CM_DSI0ECTL_KILL_BITS                              5:5
      #define CM_DSI0ECTL_KILL_SET                               0x00000020
      #define CM_DSI0ECTL_KILL_CLR                               0xffffffdf
      #define CM_DSI0ECTL_KILL_MSB                               5
      #define CM_DSI0ECTL_KILL_LSB                               5
      #define CM_DSI0ECTL_ENAB_BITS                              4:4
      #define CM_DSI0ECTL_ENAB_SET                               0x00000010
      #define CM_DSI0ECTL_ENAB_CLR                               0xffffffef
      #define CM_DSI0ECTL_ENAB_MSB                               4
      #define CM_DSI0ECTL_ENAB_LSB                               4
      #define CM_DSI0ECTL_SRC_BITS                               3:0
      #define CM_DSI0ECTL_SRC_SET                                0x0000000f
      #define CM_DSI0ECTL_SRC_CLR                                0xfffffff0
      #define CM_DSI0ECTL_SRC_MSB                                3
      #define CM_DSI0ECTL_SRC_LSB                                0
#define CM_DSI0EDIV                                              HW_REGISTER_RW( 0x7e10105c ) 
   #define CM_DSI0EDIV_MASK                                      0x0000fff0
   #define CM_DSI0EDIV_WIDTH                                     16
   #define CM_DSI0EDIV_RESET                                     0000000000
      #define CM_DSI0EDIV_DIV_BITS                               15:4
      #define CM_DSI0EDIV_DIV_SET                                0x0000fff0
      #define CM_DSI0EDIV_DIV_CLR                                0xffff000f
      #define CM_DSI0EDIV_DIV_MSB                                15
      #define CM_DSI0EDIV_DIV_LSB                                4
#define CM_DSI0PCTL                                              HW_REGISTER_RW( 0x7e101060 ) 
   #define CM_DSI0PCTL_MASK                                      0x0000039f
   #define CM_DSI0PCTL_WIDTH                                     10
   #define CM_DSI0PCTL_RESET                                     0000000000
      #define CM_DSI0PCTL_FRAC_BITS                              9:9
      #define CM_DSI0PCTL_FRAC_SET                               0x00000200
      #define CM_DSI0PCTL_FRAC_CLR                               0xfffffdff
      #define CM_DSI0PCTL_FRAC_MSB                               9
      #define CM_DSI0PCTL_FRAC_LSB                               9
      #define CM_DSI0PCTL_BUSYD_BITS                             8:8
      #define CM_DSI0PCTL_BUSYD_SET                              0x00000100
      #define CM_DSI0PCTL_BUSYD_CLR                              0xfffffeff
      #define CM_DSI0PCTL_BUSYD_MSB                              8
      #define CM_DSI0PCTL_BUSYD_LSB                              8
      #define CM_DSI0PCTL_BUSY_BITS                              7:7
      #define CM_DSI0PCTL_BUSY_SET                               0x00000080
      #define CM_DSI0PCTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI0PCTL_BUSY_MSB                               7
      #define CM_DSI0PCTL_BUSY_LSB                               7
      #define CM_DSI0PCTL_ENAB_BITS                              4:4
      #define CM_DSI0PCTL_ENAB_SET                               0x00000010
      #define CM_DSI0PCTL_ENAB_CLR                               0xffffffef
      #define CM_DSI0PCTL_ENAB_MSB                               4
      #define CM_DSI0PCTL_ENAB_LSB                               4
      #define CM_DSI0PCTL_SRC_BITS                               3:0
      #define CM_DSI0PCTL_SRC_SET                                0x0000000f
      #define CM_DSI0PCTL_SRC_CLR                                0xfffffff0
      #define CM_DSI0PCTL_SRC_MSB                                3
      #define CM_DSI0PCTL_SRC_LSB                                0
#define CM_DSI0PDIV                                              HW_REGISTER_RO( 0x7e101064 ) 
   #define CM_DSI0PDIV_MASK                                      0x00001000
   #define CM_DSI0PDIV_WIDTH                                     13
   #define CM_DSI0PDIV_RESET                                     0x00001000
      #define CM_DSI0PDIV_DIV_BITS                               12:12
      #define CM_DSI0PDIV_DIV_SET                                0x00001000
      #define CM_DSI0PDIV_DIV_CLR                                0xffffefff
      #define CM_DSI0PDIV_DIV_MSB                                12
      #define CM_DSI0PDIV_DIV_LSB                                12
#define CM_DSI1ECTL                                              HW_REGISTER_RW( 0x7e101158 ) 
   #define CM_DSI1ECTL_MASK                                      0x000003bf
   #define CM_DSI1ECTL_WIDTH                                     10
   #define CM_DSI1ECTL_RESET                                     0000000000
      #define CM_DSI1ECTL_FRAC_BITS                              9:9
      #define CM_DSI1ECTL_FRAC_SET                               0x00000200
      #define CM_DSI1ECTL_FRAC_CLR                               0xfffffdff
      #define CM_DSI1ECTL_FRAC_MSB                               9
      #define CM_DSI1ECTL_FRAC_LSB                               9
      #define CM_DSI1ECTL_BUSYD_BITS                             8:8
      #define CM_DSI1ECTL_BUSYD_SET                              0x00000100
      #define CM_DSI1ECTL_BUSYD_CLR                              0xfffffeff
      #define CM_DSI1ECTL_BUSYD_MSB                              8
      #define CM_DSI1ECTL_BUSYD_LSB                              8
      #define CM_DSI1ECTL_BUSY_BITS                              7:7
      #define CM_DSI1ECTL_BUSY_SET                               0x00000080
      #define CM_DSI1ECTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI1ECTL_BUSY_MSB                               7
      #define CM_DSI1ECTL_BUSY_LSB                               7
      #define CM_DSI1ECTL_KILL_BITS                              5:5
      #define CM_DSI1ECTL_KILL_SET                               0x00000020
      #define CM_DSI1ECTL_KILL_CLR                               0xffffffdf
      #define CM_DSI1ECTL_KILL_MSB                               5
      #define CM_DSI1ECTL_KILL_LSB                               5
      #define CM_DSI1ECTL_ENAB_BITS                              4:4
      #define CM_DSI1ECTL_ENAB_SET                               0x00000010
      #define CM_DSI1ECTL_ENAB_CLR                               0xffffffef
      #define CM_DSI1ECTL_ENAB_MSB                               4
      #define CM_DSI1ECTL_ENAB_LSB                               4
      #define CM_DSI1ECTL_SRC_BITS                               3:0
      #define CM_DSI1ECTL_SRC_SET                                0x0000000f
      #define CM_DSI1ECTL_SRC_CLR                                0xfffffff0
      #define CM_DSI1ECTL_SRC_MSB                                3
      #define CM_DSI1ECTL_SRC_LSB                                0
#define CM_DSI1EDIV                                              HW_REGISTER_RW( 0x7e10115c ) 
   #define CM_DSI1EDIV_MASK                                      0x0000fff0
   #define CM_DSI1EDIV_WIDTH                                     16
   #define CM_DSI1EDIV_RESET                                     0000000000
      #define CM_DSI1EDIV_DIV_BITS                               15:4
      #define CM_DSI1EDIV_DIV_SET                                0x0000fff0
      #define CM_DSI1EDIV_DIV_CLR                                0xffff000f
      #define CM_DSI1EDIV_DIV_MSB                                15
      #define CM_DSI1EDIV_DIV_LSB                                4
#define CM_DSI1PCTL                                              HW_REGISTER_RW( 0x7e101160 ) 
   #define CM_DSI1PCTL_MASK                                      0x0000039f
   #define CM_DSI1PCTL_WIDTH                                     10
   #define CM_DSI1PCTL_RESET                                     0000000000
      #define CM_DSI1PCTL_FRAC_BITS                              9:9
      #define CM_DSI1PCTL_FRAC_SET                               0x00000200
      #define CM_DSI1PCTL_FRAC_CLR                               0xfffffdff
      #define CM_DSI1PCTL_FRAC_MSB                               9
      #define CM_DSI1PCTL_FRAC_LSB                               9
      #define CM_DSI1PCTL_BUSYD_BITS                             8:8
      #define CM_DSI1PCTL_BUSYD_SET                              0x00000100
      #define CM_DSI1PCTL_BUSYD_CLR                              0xfffffeff
      #define CM_DSI1PCTL_BUSYD_MSB                              8
      #define CM_DSI1PCTL_BUSYD_LSB                              8
      #define CM_DSI1PCTL_BUSY_BITS                              7:7
      #define CM_DSI1PCTL_BUSY_SET                               0x00000080
      #define CM_DSI1PCTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI1PCTL_BUSY_MSB                               7
      #define CM_DSI1PCTL_BUSY_LSB                               7
      #define CM_DSI1PCTL_ENAB_BITS                              4:4
      #define CM_DSI1PCTL_ENAB_SET                               0x00000010
      #define CM_DSI1PCTL_ENAB_CLR                               0xffffffef
      #define CM_DSI1PCTL_ENAB_MSB                               4
      #define CM_DSI1PCTL_ENAB_LSB                               4
      #define CM_DSI1PCTL_SRC_BITS                               3:0
      #define CM_DSI1PCTL_SRC_SET                                0x0000000f
      #define CM_DSI1PCTL_SRC_CLR                                0xfffffff0
      #define CM_DSI1PCTL_SRC_MSB                                3
      #define CM_DSI1PCTL_SRC_LSB                                0
#define CM_DSI1PDIV                                              HW_REGISTER_RO( 0x7e101164 ) 
   #define CM_DSI1PDIV_MASK                                      0x00001000
   #define CM_DSI1PDIV_WIDTH                                     13
   #define CM_DSI1PDIV_RESET                                     0x00001000
      #define CM_DSI1PDIV_DIV_BITS                               12:12
      #define CM_DSI1PDIV_DIV_SET                                0x00001000
      #define CM_DSI1PDIV_DIV_CLR                                0xffffefff
      #define CM_DSI1PDIV_DIV_MSB                                12
      #define CM_DSI1PDIV_DIV_LSB                                12
#define CM_DPICTL                                                HW_REGISTER_RW( 0x7e101068 ) 
   #define CM_DPICTL_MASK                                        0x000003bf
   #define CM_DPICTL_WIDTH                                       10
   #define CM_DPICTL_RESET                                       0000000000
      #define CM_DPICTL_FRAC_BITS                                9:9
      #define CM_DPICTL_FRAC_SET                                 0x00000200
      #define CM_DPICTL_FRAC_CLR                                 0xfffffdff
      #define CM_DPICTL_FRAC_MSB                                 9
      #define CM_DPICTL_FRAC_LSB                                 9
      #define CM_DPICTL_BUSYD_BITS                               8:8
      #define CM_DPICTL_BUSYD_SET                                0x00000100
      #define CM_DPICTL_BUSYD_CLR                                0xfffffeff
      #define CM_DPICTL_BUSYD_MSB                                8
      #define CM_DPICTL_BUSYD_LSB                                8
      #define CM_DPICTL_BUSY_BITS                                7:7
      #define CM_DPICTL_BUSY_SET                                 0x00000080
      #define CM_DPICTL_BUSY_CLR                                 0xffffff7f
      #define CM_DPICTL_BUSY_MSB                                 7
      #define CM_DPICTL_BUSY_LSB                                 7
      #define CM_DPICTL_KILL_BITS                                5:5
      #define CM_DPICTL_KILL_SET                                 0x00000020
      #define CM_DPICTL_KILL_CLR                                 0xffffffdf
      #define CM_DPICTL_KILL_MSB                                 5
      #define CM_DPICTL_KILL_LSB                                 5
      #define CM_DPICTL_ENAB_BITS                                4:4
      #define CM_DPICTL_ENAB_SET                                 0x00000010
      #define CM_DPICTL_ENAB_CLR                                 0xffffffef
      #define CM_DPICTL_ENAB_MSB                                 4
      #define CM_DPICTL_ENAB_LSB                                 4
      #define CM_DPICTL_SRC_BITS                                 3:0
      #define CM_DPICTL_SRC_SET                                  0x0000000f
      #define CM_DPICTL_SRC_CLR                                  0xfffffff0
      #define CM_DPICTL_SRC_MSB                                  3
      #define CM_DPICTL_SRC_LSB                                  0
#define CM_DPIDIV                                                HW_REGISTER_RW( 0x7e10106c ) 
   #define CM_DPIDIV_MASK                                        0x0000fff0
   #define CM_DPIDIV_WIDTH                                       16
   #define CM_DPIDIV_RESET                                       0000000000
      #define CM_DPIDIV_DIV_BITS                                 15:4
      #define CM_DPIDIV_DIV_SET                                  0x0000fff0
      #define CM_DPIDIV_DIV_CLR                                  0xffff000f
      #define CM_DPIDIV_DIV_MSB                                  15
      #define CM_DPIDIV_DIV_LSB                                  4
#define CM_DFTCTL                                                HW_REGISTER_RW( 0x7e101168 ) 
   #define CM_DFTCTL_MASK                                        0x000003bf
   #define CM_DFTCTL_WIDTH                                       10
   #define CM_DFTCTL_RESET                                       0000000000
      #define CM_DFTCTL_FRAC_BITS                                9:9
      #define CM_DFTCTL_FRAC_SET                                 0x00000200
      #define CM_DFTCTL_FRAC_CLR                                 0xfffffdff
      #define CM_DFTCTL_FRAC_MSB                                 9
      #define CM_DFTCTL_FRAC_LSB                                 9
      #define CM_DFTCTL_BUSYD_BITS                               8:8
      #define CM_DFTCTL_BUSYD_SET                                0x00000100
      #define CM_DFTCTL_BUSYD_CLR                                0xfffffeff
      #define CM_DFTCTL_BUSYD_MSB                                8
      #define CM_DFTCTL_BUSYD_LSB                                8
      #define CM_DFTCTL_BUSY_BITS                                7:7
      #define CM_DFTCTL_BUSY_SET                                 0x00000080
      #define CM_DFTCTL_BUSY_CLR                                 0xffffff7f
      #define CM_DFTCTL_BUSY_MSB                                 7
      #define CM_DFTCTL_BUSY_LSB                                 7
      #define CM_DFTCTL_KILL_BITS                                5:5
      #define CM_DFTCTL_KILL_SET                                 0x00000020
      #define CM_DFTCTL_KILL_CLR                                 0xffffffdf
      #define CM_DFTCTL_KILL_MSB                                 5
      #define CM_DFTCTL_KILL_LSB                                 5
      #define CM_DFTCTL_ENAB_BITS                                4:4
      #define CM_DFTCTL_ENAB_SET                                 0x00000010
      #define CM_DFTCTL_ENAB_CLR                                 0xffffffef
      #define CM_DFTCTL_ENAB_MSB                                 4
      #define CM_DFTCTL_ENAB_LSB                                 4
      #define CM_DFTCTL_SRC_BITS                                 3:0
      #define CM_DFTCTL_SRC_SET                                  0x0000000f
      #define CM_DFTCTL_SRC_CLR                                  0xfffffff0
      #define CM_DFTCTL_SRC_MSB                                  3
      #define CM_DFTCTL_SRC_LSB                                  0
#define CM_DFTDIV                                                HW_REGISTER_RW( 0x7e10116c ) 
   #define CM_DFTDIV_MASK                                        0x0001f000
   #define CM_DFTDIV_WIDTH                                       17
   #define CM_DFTDIV_RESET                                       0000000000
      #define CM_DFTDIV_DIV_BITS                                 16:12
      #define CM_DFTDIV_DIV_SET                                  0x0001f000
      #define CM_DFTDIV_DIV_CLR                                  0xfffe0fff
      #define CM_DFTDIV_DIV_MSB                                  16
      #define CM_DFTDIV_DIV_LSB                                  12
#define CM_GP0CTL                                                HW_REGISTER_RW( 0x7e101070 ) 
   #define CM_GP0CTL_MASK                                        0x000007bf
   #define CM_GP0CTL_WIDTH                                       11
   #define CM_GP0CTL_RESET                                       0x00000200
      #define CM_GP0CTL_MASH_BITS                                10:9
      #define CM_GP0CTL_MASH_SET                                 0x00000600
      #define CM_GP0CTL_MASH_CLR                                 0xfffff9ff
      #define CM_GP0CTL_MASH_MSB                                 10
      #define CM_GP0CTL_MASH_LSB                                 9
      #define CM_GP0CTL_BUSYD_BITS                               8:8
      #define CM_GP0CTL_BUSYD_SET                                0x00000100
      #define CM_GP0CTL_BUSYD_CLR                                0xfffffeff
      #define CM_GP0CTL_BUSYD_MSB                                8
      #define CM_GP0CTL_BUSYD_LSB                                8
      #define CM_GP0CTL_BUSY_BITS                                7:7
      #define CM_GP0CTL_BUSY_SET                                 0x00000080
      #define CM_GP0CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP0CTL_BUSY_MSB                                 7
      #define CM_GP0CTL_BUSY_LSB                                 7
      #define CM_GP0CTL_KILL_BITS                                5:5
      #define CM_GP0CTL_KILL_SET                                 0x00000020
      #define CM_GP0CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP0CTL_KILL_MSB                                 5
      #define CM_GP0CTL_KILL_LSB                                 5
      #define CM_GP0CTL_ENAB_BITS                                4:4
      #define CM_GP0CTL_ENAB_SET                                 0x00000010
      #define CM_GP0CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP0CTL_ENAB_MSB                                 4
      #define CM_GP0CTL_ENAB_LSB                                 4
      #define CM_GP0CTL_SRC_BITS                                 3:0
      #define CM_GP0CTL_SRC_SET                                  0x0000000f
      #define CM_GP0CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP0CTL_SRC_MSB                                  3
      #define CM_GP0CTL_SRC_LSB                                  0
#define CM_GP0DIV                                                HW_REGISTER_RW( 0x7e101074 ) 
   #define CM_GP0DIV_MASK                                        0x00ffffff
   #define CM_GP0DIV_WIDTH                                       24
   #define CM_GP0DIV_RESET                                       0000000000
      #define CM_GP0DIV_DIV_BITS                                 23:0
      #define CM_GP0DIV_DIV_SET                                  0x00ffffff
      #define CM_GP0DIV_DIV_CLR                                  0xff000000
      #define CM_GP0DIV_DIV_MSB                                  23
      #define CM_GP0DIV_DIV_LSB                                  0
#define CM_GP1CTL                                                HW_REGISTER_RW( 0x7e101078 ) 
   #define CM_GP1CTL_MASK                                        0x000007bf
   #define CM_GP1CTL_WIDTH                                       11
   #define CM_GP1CTL_RESET                                       0x00000200
      #define CM_GP1CTL_MASH_BITS                                10:9
      #define CM_GP1CTL_MASH_SET                                 0x00000600
      #define CM_GP1CTL_MASH_CLR                                 0xfffff9ff
      #define CM_GP1CTL_MASH_MSB                                 10
      #define CM_GP1CTL_MASH_LSB                                 9
      #define CM_GP1CTL_BUSYD_BITS                               8:8
      #define CM_GP1CTL_BUSYD_SET                                0x00000100
      #define CM_GP1CTL_BUSYD_CLR                                0xfffffeff
      #define CM_GP1CTL_BUSYD_MSB                                8
      #define CM_GP1CTL_BUSYD_LSB                                8
      #define CM_GP1CTL_BUSY_BITS                                7:7
      #define CM_GP1CTL_BUSY_SET                                 0x00000080
      #define CM_GP1CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP1CTL_BUSY_MSB                                 7
      #define CM_GP1CTL_BUSY_LSB                                 7
      #define CM_GP1CTL_KILL_BITS                                5:5
      #define CM_GP1CTL_KILL_SET                                 0x00000020
      #define CM_GP1CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP1CTL_KILL_MSB                                 5
      #define CM_GP1CTL_KILL_LSB                                 5
      #define CM_GP1CTL_ENAB_BITS                                4:4
      #define CM_GP1CTL_ENAB_SET                                 0x00000010
      #define CM_GP1CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP1CTL_ENAB_MSB                                 4
      #define CM_GP1CTL_ENAB_LSB                                 4
      #define CM_GP1CTL_SRC_BITS                                 3:0
      #define CM_GP1CTL_SRC_SET                                  0x0000000f
      #define CM_GP1CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP1CTL_SRC_MSB                                  3
      #define CM_GP1CTL_SRC_LSB                                  0
#define CM_GP1DIV                                                HW_REGISTER_RW( 0x7e10107c ) 
   #define CM_GP1DIV_MASK                                        0x00ffffff
   #define CM_GP1DIV_WIDTH                                       24
   #define CM_GP1DIV_RESET                                       0000000000
      #define CM_GP1DIV_DIV_BITS                                 23:0
      #define CM_GP1DIV_DIV_SET                                  0x00ffffff
      #define CM_GP1DIV_DIV_CLR                                  0xff000000
      #define CM_GP1DIV_DIV_MSB                                  23
      #define CM_GP1DIV_DIV_LSB                                  0
#define CM_GP2CTL                                                HW_REGISTER_RW( 0x7e101080 ) 
   #define CM_GP2CTL_MASK                                        0x000003bf
   #define CM_GP2CTL_WIDTH                                       10
   #define CM_GP2CTL_RESET                                       0000000000
      #define CM_GP2CTL_FRAC_BITS                                9:9
      #define CM_GP2CTL_FRAC_SET                                 0x00000200
      #define CM_GP2CTL_FRAC_CLR                                 0xfffffdff
      #define CM_GP2CTL_FRAC_MSB                                 9
      #define CM_GP2CTL_FRAC_LSB                                 9
      #define CM_GP2CTL_BUSYD_BITS                               8:8
      #define CM_GP2CTL_BUSYD_SET                                0x00000100
      #define CM_GP2CTL_BUSYD_CLR                                0xfffffeff
      #define CM_GP2CTL_BUSYD_MSB                                8
      #define CM_GP2CTL_BUSYD_LSB                                8
      #define CM_GP2CTL_BUSY_BITS                                7:7
      #define CM_GP2CTL_BUSY_SET                                 0x00000080
      #define CM_GP2CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP2CTL_BUSY_MSB                                 7
      #define CM_GP2CTL_BUSY_LSB                                 7
      #define CM_GP2CTL_KILL_BITS                                5:5
      #define CM_GP2CTL_KILL_SET                                 0x00000020
      #define CM_GP2CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP2CTL_KILL_MSB                                 5
      #define CM_GP2CTL_KILL_LSB                                 5
      #define CM_GP2CTL_ENAB_BITS                                4:4
      #define CM_GP2CTL_ENAB_SET                                 0x00000010
      #define CM_GP2CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP2CTL_ENAB_MSB                                 4
      #define CM_GP2CTL_ENAB_LSB                                 4
      #define CM_GP2CTL_SRC_BITS                                 3:0
      #define CM_GP2CTL_SRC_SET                                  0x0000000f
      #define CM_GP2CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP2CTL_SRC_MSB                                  3
      #define CM_GP2CTL_SRC_LSB                                  0
#define CM_GP2DIV                                                HW_REGISTER_RW( 0x7e101084 ) 
   #define CM_GP2DIV_MASK                                        0x00ffffff
   #define CM_GP2DIV_WIDTH                                       24
   #define CM_GP2DIV_RESET                                       0000000000
      #define CM_GP2DIV_DIV_BITS                                 23:0
      #define CM_GP2DIV_DIV_SET                                  0x00ffffff
      #define CM_GP2DIV_DIV_CLR                                  0xff000000
      #define CM_GP2DIV_DIV_MSB                                  23
      #define CM_GP2DIV_DIV_LSB                                  0
#define CM_HSMCTL                                                HW_REGISTER_RW( 0x7e101088 ) 
   #define CM_HSMCTL_MASK                                        0x000003ff
   #define CM_HSMCTL_WIDTH                                       10
   #define CM_HSMCTL_RESET                                       0000000000
      #define CM_HSMCTL_FRAC_BITS                                9:9
      #define CM_HSMCTL_FRAC_SET                                 0x00000200
      #define CM_HSMCTL_FRAC_CLR                                 0xfffffdff
      #define CM_HSMCTL_FRAC_MSB                                 9
      #define CM_HSMCTL_FRAC_LSB                                 9
      #define CM_HSMCTL_BUSYD_BITS                               8:8
      #define CM_HSMCTL_BUSYD_SET                                0x00000100
      #define CM_HSMCTL_BUSYD_CLR                                0xfffffeff
      #define CM_HSMCTL_BUSYD_MSB                                8
      #define CM_HSMCTL_BUSYD_LSB                                8
      #define CM_HSMCTL_BUSY_BITS                                7:7
      #define CM_HSMCTL_BUSY_SET                                 0x00000080
      #define CM_HSMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_HSMCTL_BUSY_MSB                                 7
      #define CM_HSMCTL_BUSY_LSB                                 7
      #define CM_HSMCTL_GATE_BITS                                6:6
      #define CM_HSMCTL_GATE_SET                                 0x00000040
      #define CM_HSMCTL_GATE_CLR                                 0xffffffbf
      #define CM_HSMCTL_GATE_MSB                                 6
      #define CM_HSMCTL_GATE_LSB                                 6
      #define CM_HSMCTL_KILL_BITS                                5:5
      #define CM_HSMCTL_KILL_SET                                 0x00000020
      #define CM_HSMCTL_KILL_CLR                                 0xffffffdf
      #define CM_HSMCTL_KILL_MSB                                 5
      #define CM_HSMCTL_KILL_LSB                                 5
      #define CM_HSMCTL_ENAB_BITS                                4:4
      #define CM_HSMCTL_ENAB_SET                                 0x00000010
      #define CM_HSMCTL_ENAB_CLR                                 0xffffffef
      #define CM_HSMCTL_ENAB_MSB                                 4
      #define CM_HSMCTL_ENAB_LSB                                 4
      #define CM_HSMCTL_SRC_BITS                                 3:0
      #define CM_HSMCTL_SRC_SET                                  0x0000000f
      #define CM_HSMCTL_SRC_CLR                                  0xfffffff0
      #define CM_HSMCTL_SRC_MSB                                  3
      #define CM_HSMCTL_SRC_LSB                                  0
#define CM_HSMDIV                                                HW_REGISTER_RW( 0x7e10108c ) 
   #define CM_HSMDIV_MASK                                        0x0000fff0
   #define CM_HSMDIV_WIDTH                                       16
   #define CM_HSMDIV_RESET                                       0000000000
      #define CM_HSMDIV_DIV_BITS                                 15:4
      #define CM_HSMDIV_DIV_SET                                  0x0000fff0
      #define CM_HSMDIV_DIV_CLR                                  0xffff000f
      #define CM_HSMDIV_DIV_MSB                                  15
      #define CM_HSMDIV_DIV_LSB                                  4
#define CM_OTPCTL                                                HW_REGISTER_RW( 0x7e101090 ) 
   #define CM_OTPCTL_MASK                                        0x000003b3
   #define CM_OTPCTL_WIDTH                                       10
   #define CM_OTPCTL_RESET                                       0x00000011
      #define CM_OTPCTL_FRAC_BITS                                9:9
      #define CM_OTPCTL_FRAC_SET                                 0x00000200
      #define CM_OTPCTL_FRAC_CLR                                 0xfffffdff
      #define CM_OTPCTL_FRAC_MSB                                 9
      #define CM_OTPCTL_FRAC_LSB                                 9
      #define CM_OTPCTL_BUSYD_BITS                               8:8
      #define CM_OTPCTL_BUSYD_SET                                0x00000100
      #define CM_OTPCTL_BUSYD_CLR                                0xfffffeff
      #define CM_OTPCTL_BUSYD_MSB                                8
      #define CM_OTPCTL_BUSYD_LSB                                8
      #define CM_OTPCTL_BUSY_BITS                                7:7
      #define CM_OTPCTL_BUSY_SET                                 0x00000080
      #define CM_OTPCTL_BUSY_CLR                                 0xffffff7f
      #define CM_OTPCTL_BUSY_MSB                                 7
      #define CM_OTPCTL_BUSY_LSB                                 7
      #define CM_OTPCTL_KILL_BITS                                5:5
      #define CM_OTPCTL_KILL_SET                                 0x00000020
      #define CM_OTPCTL_KILL_CLR                                 0xffffffdf
      #define CM_OTPCTL_KILL_MSB                                 5
      #define CM_OTPCTL_KILL_LSB                                 5
      #define CM_OTPCTL_ENAB_BITS                                4:4
      #define CM_OTPCTL_ENAB_SET                                 0x00000010
      #define CM_OTPCTL_ENAB_CLR                                 0xffffffef
      #define CM_OTPCTL_ENAB_MSB                                 4
      #define CM_OTPCTL_ENAB_LSB                                 4
      #define CM_OTPCTL_SRC_BITS                                 1:0
      #define CM_OTPCTL_SRC_SET                                  0x00000003
      #define CM_OTPCTL_SRC_CLR                                  0xfffffffc
      #define CM_OTPCTL_SRC_MSB                                  1
      #define CM_OTPCTL_SRC_LSB                                  0
#define CM_OTPDIV                                                HW_REGISTER_RW( 0x7e101094 ) 
   #define CM_OTPDIV_MASK                                        0x0001f000
   #define CM_OTPDIV_WIDTH                                       17
   #define CM_OTPDIV_RESET                                       0x00004000
      #define CM_OTPDIV_DIV_BITS                                 16:12
      #define CM_OTPDIV_DIV_SET                                  0x0001f000
      #define CM_OTPDIV_DIV_CLR                                  0xfffe0fff
      #define CM_OTPDIV_DIV_MSB                                  16
      #define CM_OTPDIV_DIV_LSB                                  12
#define CM_PULSECTL                                              HW_REGISTER_RW( 0x7e101190 ) 
   #define CM_PULSECTL_MASK                                      0x000003b3
   #define CM_PULSECTL_WIDTH                                     10
   #define CM_PULSECTL_RESET                                     0x00000011
      #define CM_PULSECTL_FRAC_BITS                              9:9
      #define CM_PULSECTL_FRAC_SET                               0x00000200
      #define CM_PULSECTL_FRAC_CLR                               0xfffffdff
      #define CM_PULSECTL_FRAC_MSB                               9
      #define CM_PULSECTL_FRAC_LSB                               9
      #define CM_PULSECTL_BUSYD_BITS                             8:8
      #define CM_PULSECTL_BUSYD_SET                              0x00000100
      #define CM_PULSECTL_BUSYD_CLR                              0xfffffeff
      #define CM_PULSECTL_BUSYD_MSB                              8
      #define CM_PULSECTL_BUSYD_LSB                              8
      #define CM_PULSECTL_BUSY_BITS                              7:7
      #define CM_PULSECTL_BUSY_SET                               0x00000080
      #define CM_PULSECTL_BUSY_CLR                               0xffffff7f
      #define CM_PULSECTL_BUSY_MSB                               7
      #define CM_PULSECTL_BUSY_LSB                               7
      #define CM_PULSECTL_KILL_BITS                              5:5
      #define CM_PULSECTL_KILL_SET                               0x00000020
      #define CM_PULSECTL_KILL_CLR                               0xffffffdf
      #define CM_PULSECTL_KILL_MSB                               5
      #define CM_PULSECTL_KILL_LSB                               5
      #define CM_PULSECTL_ENAB_BITS                              4:4
      #define CM_PULSECTL_ENAB_SET                               0x00000010
      #define CM_PULSECTL_ENAB_CLR                               0xffffffef
      #define CM_PULSECTL_ENAB_MSB                               4
      #define CM_PULSECTL_ENAB_LSB                               4
      #define CM_PULSECTL_SRC_BITS                               1:0
      #define CM_PULSECTL_SRC_SET                                0x00000003
      #define CM_PULSECTL_SRC_CLR                                0xfffffffc
      #define CM_PULSECTL_SRC_MSB                                1
      #define CM_PULSECTL_SRC_LSB                                0
#define CM_PULSEDIV                                              HW_REGISTER_RW( 0x7e101194 ) 
   #define CM_PULSEDIV_MASK                                      0x00fff000
   #define CM_PULSEDIV_WIDTH                                     24
   #define CM_PULSEDIV_RESET                                     0x00014000
      #define CM_PULSEDIV_DIV_BITS                               23:12
      #define CM_PULSEDIV_DIV_SET                                0x00fff000
      #define CM_PULSEDIV_DIV_CLR                                0xff000fff
      #define CM_PULSEDIV_DIV_MSB                                23
      #define CM_PULSEDIV_DIV_LSB                                12
#define CM_PCMCTL                                                HW_REGISTER_RW( 0x7e101098 ) 
   #define CM_PCMCTL_MASK                                        0x000007bf
   #define CM_PCMCTL_WIDTH                                       11
   #define CM_PCMCTL_RESET                                       0x00000200
      #define CM_PCMCTL_MASH_BITS                                10:9
      #define CM_PCMCTL_MASH_SET                                 0x00000600
      #define CM_PCMCTL_MASH_CLR                                 0xfffff9ff
      #define CM_PCMCTL_MASH_MSB                                 10
      #define CM_PCMCTL_MASH_LSB                                 9
      #define CM_PCMCTL_BUSYD_BITS                               8:8
      #define CM_PCMCTL_BUSYD_SET                                0x00000100
      #define CM_PCMCTL_BUSYD_CLR                                0xfffffeff
      #define CM_PCMCTL_BUSYD_MSB                                8
      #define CM_PCMCTL_BUSYD_LSB                                8
      #define CM_PCMCTL_BUSY_BITS                                7:7
      #define CM_PCMCTL_BUSY_SET                                 0x00000080
      #define CM_PCMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_PCMCTL_BUSY_MSB                                 7
      #define CM_PCMCTL_BUSY_LSB                                 7
      #define CM_PCMCTL_KILL_BITS                                5:5
      #define CM_PCMCTL_KILL_SET                                 0x00000020
      #define CM_PCMCTL_KILL_CLR                                 0xffffffdf
      #define CM_PCMCTL_KILL_MSB                                 5
      #define CM_PCMCTL_KILL_LSB                                 5
      #define CM_PCMCTL_ENAB_BITS                                4:4
      #define CM_PCMCTL_ENAB_SET                                 0x00000010
      #define CM_PCMCTL_ENAB_CLR                                 0xffffffef
      #define CM_PCMCTL_ENAB_MSB                                 4
      #define CM_PCMCTL_ENAB_LSB                                 4
      #define CM_PCMCTL_SRC_BITS                                 3:0
      #define CM_PCMCTL_SRC_SET                                  0x0000000f
      #define CM_PCMCTL_SRC_CLR                                  0xfffffff0
      #define CM_PCMCTL_SRC_MSB                                  3
      #define CM_PCMCTL_SRC_LSB                                  0
#define CM_PCMDIV                                                HW_REGISTER_RW( 0x7e10109c ) 
   #define CM_PCMDIV_MASK                                        0x00ffffff
   #define CM_PCMDIV_WIDTH                                       24
   #define CM_PCMDIV_RESET                                       0000000000
      #define CM_PCMDIV_DIV_BITS                                 23:0
      #define CM_PCMDIV_DIV_SET                                  0x00ffffff
      #define CM_PCMDIV_DIV_CLR                                  0xff000000
      #define CM_PCMDIV_DIV_MSB                                  23
      #define CM_PCMDIV_DIV_LSB                                  0
#define CM_PWMCTL                                                HW_REGISTER_RW( 0x7e1010a0 ) 
   #define CM_PWMCTL_MASK                                        0x000007bf
   #define CM_PWMCTL_WIDTH                                       11
   #define CM_PWMCTL_RESET                                       0x00000200
      #define CM_PWMCTL_MASH_BITS                                10:9
      #define CM_PWMCTL_MASH_SET                                 0x00000600
      #define CM_PWMCTL_MASH_CLR                                 0xfffff9ff
      #define CM_PWMCTL_MASH_MSB                                 10
      #define CM_PWMCTL_MASH_LSB                                 9
      #define CM_PWMCTL_BUSYD_BITS                               8:8
      #define CM_PWMCTL_BUSYD_SET                                0x00000100
      #define CM_PWMCTL_BUSYD_CLR                                0xfffffeff
      #define CM_PWMCTL_BUSYD_MSB                                8
      #define CM_PWMCTL_BUSYD_LSB                                8
      #define CM_PWMCTL_BUSY_BITS                                7:7
      #define CM_PWMCTL_BUSY_SET                                 0x00000080
      #define CM_PWMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_PWMCTL_BUSY_MSB                                 7
      #define CM_PWMCTL_BUSY_LSB                                 7
      #define CM_PWMCTL_KILL_BITS                                5:5
      #define CM_PWMCTL_KILL_SET                                 0x00000020
      #define CM_PWMCTL_KILL_CLR                                 0xffffffdf
      #define CM_PWMCTL_KILL_MSB                                 5
      #define CM_PWMCTL_KILL_LSB                                 5
      #define CM_PWMCTL_ENAB_BITS                                4:4
      #define CM_PWMCTL_ENAB_SET                                 0x00000010
      #define CM_PWMCTL_ENAB_CLR                                 0xffffffef
      #define CM_PWMCTL_ENAB_MSB                                 4
      #define CM_PWMCTL_ENAB_LSB                                 4
      #define CM_PWMCTL_SRC_BITS                                 3:0
      #define CM_PWMCTL_SRC_SET                                  0x0000000f
      #define CM_PWMCTL_SRC_CLR                                  0xfffffff0
      #define CM_PWMCTL_SRC_MSB                                  3
      #define CM_PWMCTL_SRC_LSB                                  0
#define CM_PWMDIV                                                HW_REGISTER_RW( 0x7e1010a4 ) 
   #define CM_PWMDIV_MASK                                        0x00ffffff
   #define CM_PWMDIV_WIDTH                                       24
   #define CM_PWMDIV_RESET                                       0000000000
      #define CM_PWMDIV_DIV_BITS                                 23:0
      #define CM_PWMDIV_DIV_SET                                  0x00ffffff
      #define CM_PWMDIV_DIV_CLR                                  0xff000000
      #define CM_PWMDIV_DIV_MSB                                  23
      #define CM_PWMDIV_DIV_LSB                                  0
#define CM_SLIMCTL                                               HW_REGISTER_RW( 0x7e1010a8 ) 
   #define CM_SLIMCTL_MASK                                       0x000007bf
   #define CM_SLIMCTL_WIDTH                                      11
   #define CM_SLIMCTL_RESET                                      0x00000200
      #define CM_SLIMCTL_MASH_BITS                               10:9
      #define CM_SLIMCTL_MASH_SET                                0x00000600
      #define CM_SLIMCTL_MASH_CLR                                0xfffff9ff
      #define CM_SLIMCTL_MASH_MSB                                10
      #define CM_SLIMCTL_MASH_LSB                                9
      #define CM_SLIMCTL_BUSYD_BITS                              8:8
      #define CM_SLIMCTL_BUSYD_SET                               0x00000100
      #define CM_SLIMCTL_BUSYD_CLR                               0xfffffeff
      #define CM_SLIMCTL_BUSYD_MSB                               8
      #define CM_SLIMCTL_BUSYD_LSB                               8
      #define CM_SLIMCTL_BUSY_BITS                               7:7
      #define CM_SLIMCTL_BUSY_SET                                0x00000080
      #define CM_SLIMCTL_BUSY_CLR                                0xffffff7f
      #define CM_SLIMCTL_BUSY_MSB                                7
      #define CM_SLIMCTL_BUSY_LSB                                7
      #define CM_SLIMCTL_KILL_BITS                               5:5
      #define CM_SLIMCTL_KILL_SET                                0x00000020
      #define CM_SLIMCTL_KILL_CLR                                0xffffffdf
      #define CM_SLIMCTL_KILL_MSB                                5
      #define CM_SLIMCTL_KILL_LSB                                5
      #define CM_SLIMCTL_ENAB_BITS                               4:4
      #define CM_SLIMCTL_ENAB_SET                                0x00000010
      #define CM_SLIMCTL_ENAB_CLR                                0xffffffef
      #define CM_SLIMCTL_ENAB_MSB                                4
      #define CM_SLIMCTL_ENAB_LSB                                4
      #define CM_SLIMCTL_SRC_BITS                                3:0
      #define CM_SLIMCTL_SRC_SET                                 0x0000000f
      #define CM_SLIMCTL_SRC_CLR                                 0xfffffff0
      #define CM_SLIMCTL_SRC_MSB                                 3
      #define CM_SLIMCTL_SRC_LSB                                 0
#define CM_SLIMDIV                                               HW_REGISTER_RW( 0x7e1010ac ) 
   #define CM_SLIMDIV_MASK                                       0x00ffffff
   #define CM_SLIMDIV_WIDTH                                      24
   #define CM_SLIMDIV_RESET                                      0000000000
      #define CM_SLIMDIV_DIV_BITS                                23:0
      #define CM_SLIMDIV_DIV_SET                                 0x00ffffff
      #define CM_SLIMDIV_DIV_CLR                                 0xff000000
      #define CM_SLIMDIV_DIV_MSB                                 23
      #define CM_SLIMDIV_DIV_LSB                                 0
#define CM_SMICTL                                                HW_REGISTER_RW( 0x7e1010b0 ) 
   #define CM_SMICTL_MASK                                        0x000003bf
   #define CM_SMICTL_WIDTH                                       10
   #define CM_SMICTL_RESET                                       0000000000
      #define CM_SMICTL_FRAC_BITS                                9:9
      #define CM_SMICTL_FRAC_SET                                 0x00000200
      #define CM_SMICTL_FRAC_CLR                                 0xfffffdff
      #define CM_SMICTL_FRAC_MSB                                 9
      #define CM_SMICTL_FRAC_LSB                                 9
      #define CM_SMICTL_BUSYD_BITS                               8:8
      #define CM_SMICTL_BUSYD_SET                                0x00000100
      #define CM_SMICTL_BUSYD_CLR                                0xfffffeff
      #define CM_SMICTL_BUSYD_MSB                                8
      #define CM_SMICTL_BUSYD_LSB                                8
      #define CM_SMICTL_BUSY_BITS                                7:7
      #define CM_SMICTL_BUSY_SET                                 0x00000080
      #define CM_SMICTL_BUSY_CLR                                 0xffffff7f
      #define CM_SMICTL_BUSY_MSB                                 7
      #define CM_SMICTL_BUSY_LSB                                 7
      #define CM_SMICTL_KILL_BITS                                5:5
      #define CM_SMICTL_KILL_SET                                 0x00000020
      #define CM_SMICTL_KILL_CLR                                 0xffffffdf
      #define CM_SMICTL_KILL_MSB                                 5
      #define CM_SMICTL_KILL_LSB                                 5
      #define CM_SMICTL_ENAB_BITS                                4:4
      #define CM_SMICTL_ENAB_SET                                 0x00000010
      #define CM_SMICTL_ENAB_CLR                                 0xffffffef
      #define CM_SMICTL_ENAB_MSB                                 4
      #define CM_SMICTL_ENAB_LSB                                 4
      #define CM_SMICTL_SRC_BITS                                 3:0
      #define CM_SMICTL_SRC_SET                                  0x0000000f
      #define CM_SMICTL_SRC_CLR                                  0xfffffff0
      #define CM_SMICTL_SRC_MSB                                  3
      #define CM_SMICTL_SRC_LSB                                  0
#define CM_SMIDIV                                                HW_REGISTER_RW( 0x7e1010b4 ) 
   #define CM_SMIDIV_MASK                                        0x0000fff0
   #define CM_SMIDIV_WIDTH                                       16
   #define CM_SMIDIV_RESET                                       0000000000
      #define CM_SMIDIV_DIV_BITS                                 15:4
      #define CM_SMIDIV_DIV_SET                                  0x0000fff0
      #define CM_SMIDIV_DIV_CLR                                  0xffff000f
      #define CM_SMIDIV_DIV_MSB                                  15
      #define CM_SMIDIV_DIV_LSB                                  4
#define CM_TCNTCTL                                               HW_REGISTER_RW( 0x7e1010c0 ) 
   #define CM_TCNTCTL_MASK                                       0x000030cf
   #define CM_TCNTCTL_WIDTH                                      14
   #define CM_TCNTCTL_RESET                                      0000000000
      #define CM_TCNTCTL_SRC1_BITS                               13:12
      #define CM_TCNTCTL_SRC1_SET                                0x00003000
      #define CM_TCNTCTL_SRC1_CLR                                0xffffcfff
      #define CM_TCNTCTL_SRC1_MSB                                13
      #define CM_TCNTCTL_SRC1_LSB                                12
      #define CM_TCNTCTL_BUSY_BITS                               7:7
      #define CM_TCNTCTL_BUSY_SET                                0x00000080
      #define CM_TCNTCTL_BUSY_CLR                                0xffffff7f
      #define CM_TCNTCTL_BUSY_MSB                                7
      #define CM_TCNTCTL_BUSY_LSB                                7
      #define CM_TCNTCTL_KILL_BITS                               6:6
      #define CM_TCNTCTL_KILL_SET                                0x00000040
      #define CM_TCNTCTL_KILL_CLR                                0xffffffbf
      #define CM_TCNTCTL_KILL_MSB                                6
      #define CM_TCNTCTL_KILL_LSB                                6
      #define CM_TCNTCTL_SRC0_BITS                               3:0
      #define CM_TCNTCTL_SRC0_SET                                0x0000000f
      #define CM_TCNTCTL_SRC0_CLR                                0xfffffff0
      #define CM_TCNTCTL_SRC0_MSB                                3
      #define CM_TCNTCTL_SRC0_LSB                                0
#define CM_TCNTCNT                                               HW_REGISTER_RW( 0x7e1010c4 ) 
   #define CM_TCNTCNT_MASK                                       0x00ffffff
   #define CM_TCNTCNT_WIDTH                                      24
   #define CM_TCNTCNT_RESET                                      0000000000
      #define CM_TCNTCNT_CNT_BITS                                23:0
      #define CM_TCNTCNT_CNT_SET                                 0x00ffffff
      #define CM_TCNTCNT_CNT_CLR                                 0xff000000
      #define CM_TCNTCNT_CNT_MSB                                 23
      #define CM_TCNTCNT_CNT_LSB                                 0
#define CM_TECCTL                                                HW_REGISTER_RW( 0x7e1010c8 ) 
   #define CM_TECCTL_MASK                                        0x000003b3
   #define CM_TECCTL_WIDTH                                       10
   #define CM_TECCTL_RESET                                       0000000000
      #define CM_TECCTL_FRAC_BITS                                9:9
      #define CM_TECCTL_FRAC_SET                                 0x00000200
      #define CM_TECCTL_FRAC_CLR                                 0xfffffdff
      #define CM_TECCTL_FRAC_MSB                                 9
      #define CM_TECCTL_FRAC_LSB                                 9
      #define CM_TECCTL_BUSYD_BITS                               8:8
      #define CM_TECCTL_BUSYD_SET                                0x00000100
      #define CM_TECCTL_BUSYD_CLR                                0xfffffeff
      #define CM_TECCTL_BUSYD_MSB                                8
      #define CM_TECCTL_BUSYD_LSB                                8
      #define CM_TECCTL_BUSY_BITS                                7:7
      #define CM_TECCTL_BUSY_SET                                 0x00000080
      #define CM_TECCTL_BUSY_CLR                                 0xffffff7f
      #define CM_TECCTL_BUSY_MSB                                 7
      #define CM_TECCTL_BUSY_LSB                                 7
      #define CM_TECCTL_KILL_BITS                                5:5
      #define CM_TECCTL_KILL_SET                                 0x00000020
      #define CM_TECCTL_KILL_CLR                                 0xffffffdf
      #define CM_TECCTL_KILL_MSB                                 5
      #define CM_TECCTL_KILL_LSB                                 5
      #define CM_TECCTL_ENAB_BITS                                4:4
      #define CM_TECCTL_ENAB_SET                                 0x00000010
      #define CM_TECCTL_ENAB_CLR                                 0xffffffef
      #define CM_TECCTL_ENAB_MSB                                 4
      #define CM_TECCTL_ENAB_LSB                                 4
      #define CM_TECCTL_SRC_BITS                                 1:0
      #define CM_TECCTL_SRC_SET                                  0x00000003
      #define CM_TECCTL_SRC_CLR                                  0xfffffffc
      #define CM_TECCTL_SRC_MSB                                  1
      #define CM_TECCTL_SRC_LSB                                  0
#define CM_TECDIV                                                HW_REGISTER_RW( 0x7e1010cc ) 
   #define CM_TECDIV_MASK                                        0x0003f000
   #define CM_TECDIV_WIDTH                                       18
   #define CM_TECDIV_RESET                                       0000000000
      #define CM_TECDIV_DIV_BITS                                 17:12
      #define CM_TECDIV_DIV_SET                                  0x0003f000
      #define CM_TECDIV_DIV_CLR                                  0xfffc0fff
      #define CM_TECDIV_DIV_MSB                                  17
      #define CM_TECDIV_DIV_LSB                                  12
#define CM_TD0CTL                                                HW_REGISTER_RW( 0x7e1010d0 ) 
   #define CM_TD0CTL_MASK                                        0x00001bff
   #define CM_TD0CTL_WIDTH                                       13
   #define CM_TD0CTL_RESET                                       0000000000
      #define CM_TD0CTL_STEP_BITS                                12:12
      #define CM_TD0CTL_STEP_SET                                 0x00001000
      #define CM_TD0CTL_STEP_CLR                                 0xffffefff
      #define CM_TD0CTL_STEP_MSB                                 12
      #define CM_TD0CTL_STEP_LSB                                 12
      #define CM_TD0CTL_FLIP_BITS                                11:11
      #define CM_TD0CTL_FLIP_SET                                 0x00000800
      #define CM_TD0CTL_FLIP_CLR                                 0xfffff7ff
      #define CM_TD0CTL_FLIP_MSB                                 11
      #define CM_TD0CTL_FLIP_LSB                                 11
      #define CM_TD0CTL_FRAC_BITS                                9:9
      #define CM_TD0CTL_FRAC_SET                                 0x00000200
      #define CM_TD0CTL_FRAC_CLR                                 0xfffffdff
      #define CM_TD0CTL_FRAC_MSB                                 9
      #define CM_TD0CTL_FRAC_LSB                                 9
      #define CM_TD0CTL_BUSYD_BITS                               8:8
      #define CM_TD0CTL_BUSYD_SET                                0x00000100
      #define CM_TD0CTL_BUSYD_CLR                                0xfffffeff
      #define CM_TD0CTL_BUSYD_MSB                                8
      #define CM_TD0CTL_BUSYD_LSB                                8
      #define CM_TD0CTL_BUSY_BITS                                7:7
      #define CM_TD0CTL_BUSY_SET                                 0x00000080
      #define CM_TD0CTL_BUSY_CLR                                 0xffffff7f
      #define CM_TD0CTL_BUSY_MSB                                 7
      #define CM_TD0CTL_BUSY_LSB                                 7
      #define CM_TD0CTL_GATE_BITS                                6:6
      #define CM_TD0CTL_GATE_SET                                 0x00000040
      #define CM_TD0CTL_GATE_CLR                                 0xffffffbf
      #define CM_TD0CTL_GATE_MSB                                 6
      #define CM_TD0CTL_GATE_LSB                                 6
      #define CM_TD0CTL_KILL_BITS                                5:5
      #define CM_TD0CTL_KILL_SET                                 0x00000020
      #define CM_TD0CTL_KILL_CLR                                 0xffffffdf
      #define CM_TD0CTL_KILL_MSB                                 5
      #define CM_TD0CTL_KILL_LSB                                 5
      #define CM_TD0CTL_ENAB_BITS                                4:4
      #define CM_TD0CTL_ENAB_SET                                 0x00000010
      #define CM_TD0CTL_ENAB_CLR                                 0xffffffef
      #define CM_TD0CTL_ENAB_MSB                                 4
      #define CM_TD0CTL_ENAB_LSB                                 4
      #define CM_TD0CTL_SRC_BITS                                 3:0
      #define CM_TD0CTL_SRC_SET                                  0x0000000f
      #define CM_TD0CTL_SRC_CLR                                  0xfffffff0
      #define CM_TD0CTL_SRC_MSB                                  3
      #define CM_TD0CTL_SRC_LSB                                  0
#define CM_TD0DIV                                                HW_REGISTER_RW( 0x7e1010d4 ) 
   #define CM_TD0DIV_MASK                                        0x00ffffff
   #define CM_TD0DIV_WIDTH                                       24
   #define CM_TD0DIV_RESET                                       0000000000
      #define CM_TD0DIV_DIV_BITS                                 23:0
      #define CM_TD0DIV_DIV_SET                                  0x00ffffff
      #define CM_TD0DIV_DIV_CLR                                  0xff000000
      #define CM_TD0DIV_DIV_MSB                                  23
      #define CM_TD0DIV_DIV_LSB                                  0
#define CM_TD1CTL                                                HW_REGISTER_RW( 0x7e1010d8 ) 
   #define CM_TD1CTL_MASK                                        0x00001bff
   #define CM_TD1CTL_WIDTH                                       13
   #define CM_TD1CTL_RESET                                       0000000000
      #define CM_TD1CTL_STEP_BITS                                12:12
      #define CM_TD1CTL_STEP_SET                                 0x00001000
      #define CM_TD1CTL_STEP_CLR                                 0xffffefff
      #define CM_TD1CTL_STEP_MSB                                 12
      #define CM_TD1CTL_STEP_LSB                                 12
      #define CM_TD1CTL_FLIP_BITS                                11:11
      #define CM_TD1CTL_FLIP_SET                                 0x00000800
      #define CM_TD1CTL_FLIP_CLR                                 0xfffff7ff
      #define CM_TD1CTL_FLIP_MSB                                 11
      #define CM_TD1CTL_FLIP_LSB                                 11
      #define CM_TD1CTL_FRAC_BITS                                9:9
      #define CM_TD1CTL_FRAC_SET                                 0x00000200
      #define CM_TD1CTL_FRAC_CLR                                 0xfffffdff
      #define CM_TD1CTL_FRAC_MSB                                 9
      #define CM_TD1CTL_FRAC_LSB                                 9
      #define CM_TD1CTL_BUSYD_BITS                               8:8
      #define CM_TD1CTL_BUSYD_SET                                0x00000100
      #define CM_TD1CTL_BUSYD_CLR                                0xfffffeff
      #define CM_TD1CTL_BUSYD_MSB                                8
      #define CM_TD1CTL_BUSYD_LSB                                8
      #define CM_TD1CTL_BUSY_BITS                                7:7
      #define CM_TD1CTL_BUSY_SET                                 0x00000080
      #define CM_TD1CTL_BUSY_CLR                                 0xffffff7f
      #define CM_TD1CTL_BUSY_MSB                                 7
      #define CM_TD1CTL_BUSY_LSB                                 7
      #define CM_TD1CTL_GATE_BITS                                6:6
      #define CM_TD1CTL_GATE_SET                                 0x00000040
      #define CM_TD1CTL_GATE_CLR                                 0xffffffbf
      #define CM_TD1CTL_GATE_MSB                                 6
      #define CM_TD1CTL_GATE_LSB                                 6
      #define CM_TD1CTL_KILL_BITS                                5:5
      #define CM_TD1CTL_KILL_SET                                 0x00000020
      #define CM_TD1CTL_KILL_CLR                                 0xffffffdf
      #define CM_TD1CTL_KILL_MSB                                 5
      #define CM_TD1CTL_KILL_LSB                                 5
      #define CM_TD1CTL_ENAB_BITS                                4:4
      #define CM_TD1CTL_ENAB_SET                                 0x00000010
      #define CM_TD1CTL_ENAB_CLR                                 0xffffffef
      #define CM_TD1CTL_ENAB_MSB                                 4
      #define CM_TD1CTL_ENAB_LSB                                 4
      #define CM_TD1CTL_SRC_BITS                                 3:0
      #define CM_TD1CTL_SRC_SET                                  0x0000000f
      #define CM_TD1CTL_SRC_CLR                                  0xfffffff0
      #define CM_TD1CTL_SRC_MSB                                  3
      #define CM_TD1CTL_SRC_LSB                                  0
#define CM_TD1DIV                                                HW_REGISTER_RW( 0x7e1010dc ) 
   #define CM_TD1DIV_MASK                                        0x00ffffff
   #define CM_TD1DIV_WIDTH                                       24
   #define CM_TD1DIV_RESET                                       0000000000
      #define CM_TD1DIV_DIV_BITS                                 23:0
      #define CM_TD1DIV_DIV_SET                                  0x00ffffff
      #define CM_TD1DIV_DIV_CLR                                  0xff000000
      #define CM_TD1DIV_DIV_MSB                                  23
      #define CM_TD1DIV_DIV_LSB                                  0
#define CM_TSENSCTL                                              HW_REGISTER_RW( 0x7e1010e0 ) 
   #define CM_TSENSCTL_MASK                                      0x000003b3
   #define CM_TSENSCTL_WIDTH                                     10
   #define CM_TSENSCTL_RESET                                     0000000000
      #define CM_TSENSCTL_FRAC_BITS                              9:9
      #define CM_TSENSCTL_FRAC_SET                               0x00000200
      #define CM_TSENSCTL_FRAC_CLR                               0xfffffdff
      #define CM_TSENSCTL_FRAC_MSB                               9
      #define CM_TSENSCTL_FRAC_LSB                               9
      #define CM_TSENSCTL_BUSYD_BITS                             8:8
      #define CM_TSENSCTL_BUSYD_SET                              0x00000100
      #define CM_TSENSCTL_BUSYD_CLR                              0xfffffeff
      #define CM_TSENSCTL_BUSYD_MSB                              8
      #define CM_TSENSCTL_BUSYD_LSB                              8
      #define CM_TSENSCTL_BUSY_BITS                              7:7
      #define CM_TSENSCTL_BUSY_SET                               0x00000080
      #define CM_TSENSCTL_BUSY_CLR                               0xffffff7f
      #define CM_TSENSCTL_BUSY_MSB                               7
      #define CM_TSENSCTL_BUSY_LSB                               7
      #define CM_TSENSCTL_KILL_BITS                              5:5
      #define CM_TSENSCTL_KILL_SET                               0x00000020
      #define CM_TSENSCTL_KILL_CLR                               0xffffffdf
      #define CM_TSENSCTL_KILL_MSB                               5
      #define CM_TSENSCTL_KILL_LSB                               5
      #define CM_TSENSCTL_ENAB_BITS                              4:4
      #define CM_TSENSCTL_ENAB_SET                               0x00000010
      #define CM_TSENSCTL_ENAB_CLR                               0xffffffef
      #define CM_TSENSCTL_ENAB_MSB                               4
      #define CM_TSENSCTL_ENAB_LSB                               4
      #define CM_TSENSCTL_SRC_BITS                               1:0
      #define CM_TSENSCTL_SRC_SET                                0x00000003
      #define CM_TSENSCTL_SRC_CLR                                0xfffffffc
      #define CM_TSENSCTL_SRC_MSB                                1
      #define CM_TSENSCTL_SRC_LSB                                0
#define CM_TSENSDIV                                              HW_REGISTER_RW( 0x7e1010e4 ) 
   #define CM_TSENSDIV_MASK                                      0x0001f000
   #define CM_TSENSDIV_WIDTH                                     17
   #define CM_TSENSDIV_RESET                                     0000000000
      #define CM_TSENSDIV_DIV_BITS                               16:12
      #define CM_TSENSDIV_DIV_SET                                0x0001f000
      #define CM_TSENSDIV_DIV_CLR                                0xfffe0fff
      #define CM_TSENSDIV_DIV_MSB                                16
      #define CM_TSENSDIV_DIV_LSB                                12
#define CM_TIMERCTL                                              HW_REGISTER_RW( 0x7e1010e8 ) 
   #define CM_TIMERCTL_MASK                                      0x000003b3
   #define CM_TIMERCTL_WIDTH                                     10
   #define CM_TIMERCTL_RESET                                     0000000000
      #define CM_TIMERCTL_FRAC_BITS                              9:9
      #define CM_TIMERCTL_FRAC_SET                               0x00000200
      #define CM_TIMERCTL_FRAC_CLR                               0xfffffdff
      #define CM_TIMERCTL_FRAC_MSB                               9
      #define CM_TIMERCTL_FRAC_LSB                               9
      #define CM_TIMERCTL_BUSYD_BITS                             8:8
      #define CM_TIMERCTL_BUSYD_SET                              0x00000100
      #define CM_TIMERCTL_BUSYD_CLR                              0xfffffeff
      #define CM_TIMERCTL_BUSYD_MSB                              8
      #define CM_TIMERCTL_BUSYD_LSB                              8
      #define CM_TIMERCTL_BUSY_BITS                              7:7
      #define CM_TIMERCTL_BUSY_SET                               0x00000080
      #define CM_TIMERCTL_BUSY_CLR                               0xffffff7f
      #define CM_TIMERCTL_BUSY_MSB                               7
      #define CM_TIMERCTL_BUSY_LSB                               7
      #define CM_TIMERCTL_KILL_BITS                              5:5
      #define CM_TIMERCTL_KILL_SET                               0x00000020
      #define CM_TIMERCTL_KILL_CLR                               0xffffffdf
      #define CM_TIMERCTL_KILL_MSB                               5
      #define CM_TIMERCTL_KILL_LSB                               5
      #define CM_TIMERCTL_ENAB_BITS                              4:4
      #define CM_TIMERCTL_ENAB_SET                               0x00000010
      #define CM_TIMERCTL_ENAB_CLR                               0xffffffef
      #define CM_TIMERCTL_ENAB_MSB                               4
      #define CM_TIMERCTL_ENAB_LSB                               4
      #define CM_TIMERCTL_SRC_BITS                               1:0
      #define CM_TIMERCTL_SRC_SET                                0x00000003
      #define CM_TIMERCTL_SRC_CLR                                0xfffffffc
      #define CM_TIMERCTL_SRC_MSB                                1
      #define CM_TIMERCTL_SRC_LSB                                0
#define CM_TIMERDIV                                              HW_REGISTER_RW( 0x7e1010ec ) 
   #define CM_TIMERDIV_MASK                                      0x0003ffff
   #define CM_TIMERDIV_WIDTH                                     18
   #define CM_TIMERDIV_RESET                                     0000000000
      #define CM_TIMERDIV_DIV_BITS                               17:0
      #define CM_TIMERDIV_DIV_SET                                0x0003ffff
      #define CM_TIMERDIV_DIV_CLR                                0xfffc0000
      #define CM_TIMERDIV_DIV_MSB                                17
      #define CM_TIMERDIV_DIV_LSB                                0
#define CM_UARTCTL                                               HW_REGISTER_RW( 0x7e1010f0 ) 
   #define CM_UARTCTL_MASK                                       0x000003bf
   #define CM_UARTCTL_WIDTH                                      10
   #define CM_UARTCTL_RESET                                      0000000000
      #define CM_UARTCTL_FRAC_BITS                               9:9
      #define CM_UARTCTL_FRAC_SET                                0x00000200
      #define CM_UARTCTL_FRAC_CLR                                0xfffffdff
      #define CM_UARTCTL_FRAC_MSB                                9
      #define CM_UARTCTL_FRAC_LSB                                9
      #define CM_UARTCTL_BUSYD_BITS                              8:8
      #define CM_UARTCTL_BUSYD_SET                               0x00000100
      #define CM_UARTCTL_BUSYD_CLR                               0xfffffeff
      #define CM_UARTCTL_BUSYD_MSB                               8
      #define CM_UARTCTL_BUSYD_LSB                               8
      #define CM_UARTCTL_BUSY_BITS                               7:7
      #define CM_UARTCTL_BUSY_SET                                0x00000080
      #define CM_UARTCTL_BUSY_CLR                                0xffffff7f
      #define CM_UARTCTL_BUSY_MSB                                7
      #define CM_UARTCTL_BUSY_LSB                                7
      #define CM_UARTCTL_KILL_BITS                               5:5
      #define CM_UARTCTL_KILL_SET                                0x00000020
      #define CM_UARTCTL_KILL_CLR                                0xffffffdf
      #define CM_UARTCTL_KILL_MSB                                5
      #define CM_UARTCTL_KILL_LSB                                5
      #define CM_UARTCTL_ENAB_BITS                               4:4
      #define CM_UARTCTL_ENAB_SET                                0x00000010
      #define CM_UARTCTL_ENAB_CLR                                0xffffffef
      #define CM_UARTCTL_ENAB_MSB                                4
      #define CM_UARTCTL_ENAB_LSB                                4
      #define CM_UARTCTL_SRC_BITS                                3:0
      #define CM_UARTCTL_SRC_SET                                 0x0000000f
      #define CM_UARTCTL_SRC_CLR                                 0xfffffff0
      #define CM_UARTCTL_SRC_MSB                                 3
      #define CM_UARTCTL_SRC_LSB                                 0
#define CM_UARTDIV                                               HW_REGISTER_RW( 0x7e1010f4 ) 
   #define CM_UARTDIV_MASK                                       0x003fffff
   #define CM_UARTDIV_WIDTH                                      22
   #define CM_UARTDIV_RESET                                      0000000000
      #define CM_UARTDIV_DIV_BITS                                21:0
      #define CM_UARTDIV_DIV_SET                                 0x003fffff
      #define CM_UARTDIV_DIV_CLR                                 0xffc00000
      #define CM_UARTDIV_DIV_MSB                                 21
      #define CM_UARTDIV_DIV_LSB                                 0
#define CM_VECCTL                                                HW_REGISTER_RW( 0x7e1010f8 ) 
   #define CM_VECCTL_MASK                                        0x000003bf
   #define CM_VECCTL_WIDTH                                       10
   #define CM_VECCTL_RESET                                       0000000000
      #define CM_VECCTL_FRAC_BITS                                9:9
      #define CM_VECCTL_FRAC_SET                                 0x00000200
      #define CM_VECCTL_FRAC_CLR                                 0xfffffdff
      #define CM_VECCTL_FRAC_MSB                                 9
      #define CM_VECCTL_FRAC_LSB                                 9
      #define CM_VECCTL_BUSYD_BITS                               8:8
      #define CM_VECCTL_BUSYD_SET                                0x00000100
      #define CM_VECCTL_BUSYD_CLR                                0xfffffeff
      #define CM_VECCTL_BUSYD_MSB                                8
      #define CM_VECCTL_BUSYD_LSB                                8
      #define CM_VECCTL_BUSY_BITS                                7:7
      #define CM_VECCTL_BUSY_SET                                 0x00000080
      #define CM_VECCTL_BUSY_CLR                                 0xffffff7f
      #define CM_VECCTL_BUSY_MSB                                 7
      #define CM_VECCTL_BUSY_LSB                                 7
      #define CM_VECCTL_KILL_BITS                                5:5
      #define CM_VECCTL_KILL_SET                                 0x00000020
      #define CM_VECCTL_KILL_CLR                                 0xffffffdf
      #define CM_VECCTL_KILL_MSB                                 5
      #define CM_VECCTL_KILL_LSB                                 5
      #define CM_VECCTL_ENAB_BITS                                4:4
      #define CM_VECCTL_ENAB_SET                                 0x00000010
      #define CM_VECCTL_ENAB_CLR                                 0xffffffef
      #define CM_VECCTL_ENAB_MSB                                 4
      #define CM_VECCTL_ENAB_LSB                                 4
      #define CM_VECCTL_SRC_BITS                                 3:0
      #define CM_VECCTL_SRC_SET                                  0x0000000f
      #define CM_VECCTL_SRC_CLR                                  0xfffffff0
      #define CM_VECCTL_SRC_MSB                                  3
      #define CM_VECCTL_SRC_LSB                                  0
#define CM_VECDIV                                                HW_REGISTER_RW( 0x7e1010fc ) 
   #define CM_VECDIV_MASK                                        0x0000f000
   #define CM_VECDIV_WIDTH                                       16
   #define CM_VECDIV_RESET                                       0000000000
      #define CM_VECDIV_DIV_BITS                                 15:12
      #define CM_VECDIV_DIV_SET                                  0x0000f000
      #define CM_VECDIV_DIV_CLR                                  0xffff0fff
      #define CM_VECDIV_DIV_MSB                                  15
      #define CM_VECDIV_DIV_LSB                                  12
#define CM_AVEOCTL                                               HW_REGISTER_RW( 0x7e1011b8 ) 
   #define CM_AVEOCTL_MASK                                       0x000003bf
   #define CM_AVEOCTL_WIDTH                                      10
   #define CM_AVEOCTL_RESET                                      0000000000
      #define CM_AVEOCTL_FRAC_BITS                               9:9
      #define CM_AVEOCTL_FRAC_SET                                0x00000200
      #define CM_AVEOCTL_FRAC_CLR                                0xfffffdff
      #define CM_AVEOCTL_FRAC_MSB                                9
      #define CM_AVEOCTL_FRAC_LSB                                9
      #define CM_AVEOCTL_BUSYD_BITS                              8:8
      #define CM_AVEOCTL_BUSYD_SET                               0x00000100
      #define CM_AVEOCTL_BUSYD_CLR                               0xfffffeff
      #define CM_AVEOCTL_BUSYD_MSB                               8
      #define CM_AVEOCTL_BUSYD_LSB                               8
      #define CM_AVEOCTL_BUSY_BITS                               7:7
      #define CM_AVEOCTL_BUSY_SET                                0x00000080
      #define CM_AVEOCTL_BUSY_CLR                                0xffffff7f
      #define CM_AVEOCTL_BUSY_MSB                                7
      #define CM_AVEOCTL_BUSY_LSB                                7
      #define CM_AVEOCTL_KILL_BITS                               5:5
      #define CM_AVEOCTL_KILL_SET                                0x00000020
      #define CM_AVEOCTL_KILL_CLR                                0xffffffdf
      #define CM_AVEOCTL_KILL_MSB                                5
      #define CM_AVEOCTL_KILL_LSB                                5
      #define CM_AVEOCTL_ENAB_BITS                               4:4
      #define CM_AVEOCTL_ENAB_SET                                0x00000010
      #define CM_AVEOCTL_ENAB_CLR                                0xffffffef
      #define CM_AVEOCTL_ENAB_MSB                                4
      #define CM_AVEOCTL_ENAB_LSB                                4
      #define CM_AVEOCTL_SRC_BITS                                3:0
      #define CM_AVEOCTL_SRC_SET                                 0x0000000f
      #define CM_AVEOCTL_SRC_CLR                                 0xfffffff0
      #define CM_AVEOCTL_SRC_MSB                                 3
      #define CM_AVEOCTL_SRC_LSB                                 0
#define CM_AVEODIV                                               HW_REGISTER_RW( 0x7e1011bc ) 
   #define CM_AVEODIV_MASK                                       0x0000f000
   #define CM_AVEODIV_WIDTH                                      16
   #define CM_AVEODIV_RESET                                      0000000000
      #define CM_AVEODIV_DIV_BITS                                15:12
      #define CM_AVEODIV_DIV_SET                                 0x0000f000
      #define CM_AVEODIV_DIV_CLR                                 0xffff0fff
      #define CM_AVEODIV_DIV_MSB                                 15
      #define CM_AVEODIV_DIV_LSB                                 12
#define CM_EMMCCTL                                               HW_REGISTER_RW( 0x7e1011c0 ) 
   #define CM_EMMCCTL_MASK                                       0x000003bf
   #define CM_EMMCCTL_WIDTH                                      10
   #define CM_EMMCCTL_RESET                                      0000000000
      #define CM_EMMCCTL_FRAC_BITS                               9:9
      #define CM_EMMCCTL_FRAC_SET                                0x00000200
      #define CM_EMMCCTL_FRAC_CLR                                0xfffffdff
      #define CM_EMMCCTL_FRAC_MSB                                9
      #define CM_EMMCCTL_FRAC_LSB                                9
      #define CM_EMMCCTL_BUSYD_BITS                              8:8
      #define CM_EMMCCTL_BUSYD_SET                               0x00000100
      #define CM_EMMCCTL_BUSYD_CLR                               0xfffffeff
      #define CM_EMMCCTL_BUSYD_MSB                               8
      #define CM_EMMCCTL_BUSYD_LSB                               8
      #define CM_EMMCCTL_BUSY_BITS                               7:7
      #define CM_EMMCCTL_BUSY_SET                                0x00000080
      #define CM_EMMCCTL_BUSY_CLR                                0xffffff7f
      #define CM_EMMCCTL_BUSY_MSB                                7
      #define CM_EMMCCTL_BUSY_LSB                                7
      #define CM_EMMCCTL_KILL_BITS                               5:5
      #define CM_EMMCCTL_KILL_SET                                0x00000020
      #define CM_EMMCCTL_KILL_CLR                                0xffffffdf
      #define CM_EMMCCTL_KILL_MSB                                5
      #define CM_EMMCCTL_KILL_LSB                                5
      #define CM_EMMCCTL_ENAB_BITS                               4:4
      #define CM_EMMCCTL_ENAB_SET                                0x00000010
      #define CM_EMMCCTL_ENAB_CLR                                0xffffffef
      #define CM_EMMCCTL_ENAB_MSB                                4
      #define CM_EMMCCTL_ENAB_LSB                                4
      #define CM_EMMCCTL_SRC_BITS                                3:0
      #define CM_EMMCCTL_SRC_SET                                 0x0000000f
      #define CM_EMMCCTL_SRC_CLR                                 0xfffffff0
      #define CM_EMMCCTL_SRC_MSB                                 3
      #define CM_EMMCCTL_SRC_LSB                                 0
#define CM_EMMCDIV                                               HW_REGISTER_RW( 0x7e1011c4 ) 
   #define CM_EMMCDIV_MASK                                       0x0000fff0
   #define CM_EMMCDIV_WIDTH                                      16
   #define CM_EMMCDIV_RESET                                      0000000000
      #define CM_EMMCDIV_DIV_BITS                                15:4
      #define CM_EMMCDIV_DIV_SET                                 0x0000fff0
      #define CM_EMMCDIV_DIV_CLR                                 0xffff000f
      #define CM_EMMCDIV_DIV_MSB                                 15
      #define CM_EMMCDIV_DIV_LSB                                 4
#define CM_OSCCOUNT                                              HW_REGISTER_RW( 0x7e101100 ) 
   #define CM_OSCCOUNT_MASK                                      0x00ffffff
   #define CM_OSCCOUNT_WIDTH                                     24
   #define CM_OSCCOUNT_RESET                                     0000000000
      #define CM_OSCCOUNT_NUM_BITS                               23:0
      #define CM_OSCCOUNT_NUM_SET                                0x00ffffff
      #define CM_OSCCOUNT_NUM_CLR                                0xff000000
      #define CM_OSCCOUNT_NUM_MSB                                23
      #define CM_OSCCOUNT_NUM_LSB                                0
#define CM_PLLA                                                  HW_REGISTER_RW( 0x7e101104 ) 
   #define CM_PLLA_MASK                                          0x000003ff
   #define CM_PLLA_WIDTH                                         10
   #define CM_PLLA_RESET                                         0x00000300
      #define CM_PLLA_DIGRST_BITS                                9:9
      #define CM_PLLA_DIGRST_SET                                 0x00000200
      #define CM_PLLA_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLA_DIGRST_MSB                                 9
      #define CM_PLLA_DIGRST_LSB                                 9
      #define CM_PLLA_ANARST_BITS                                8:8
      #define CM_PLLA_ANARST_SET                                 0x00000100
      #define CM_PLLA_ANARST_CLR                                 0xfffffeff
      #define CM_PLLA_ANARST_MSB                                 8
      #define CM_PLLA_ANARST_LSB                                 8
      #define CM_PLLA_HOLDPER_BITS                               7:7
      #define CM_PLLA_HOLDPER_SET                                0x00000080
      #define CM_PLLA_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLA_HOLDPER_MSB                                7
      #define CM_PLLA_HOLDPER_LSB                                7
      #define CM_PLLA_LOADPER_BITS                               6:6
      #define CM_PLLA_LOADPER_SET                                0x00000040
      #define CM_PLLA_LOADPER_CLR                                0xffffffbf
      #define CM_PLLA_LOADPER_MSB                                6
      #define CM_PLLA_LOADPER_LSB                                6
      #define CM_PLLA_HOLDCORE_BITS                              5:5
      #define CM_PLLA_HOLDCORE_SET                               0x00000020
      #define CM_PLLA_HOLDCORE_CLR                               0xffffffdf
      #define CM_PLLA_HOLDCORE_MSB                               5
      #define CM_PLLA_HOLDCORE_LSB                               5
      #define CM_PLLA_LOADCORE_BITS                              4:4
      #define CM_PLLA_LOADCORE_SET                               0x00000010
      #define CM_PLLA_LOADCORE_CLR                               0xffffffef
      #define CM_PLLA_LOADCORE_MSB                               4
      #define CM_PLLA_LOADCORE_LSB                               4
      #define CM_PLLA_HOLDCCP2_BITS                              3:3
      #define CM_PLLA_HOLDCCP2_SET                               0x00000008
      #define CM_PLLA_HOLDCCP2_CLR                               0xfffffff7
      #define CM_PLLA_HOLDCCP2_MSB                               3
      #define CM_PLLA_HOLDCCP2_LSB                               3
      #define CM_PLLA_LOADCCP2_BITS                              2:2
      #define CM_PLLA_LOADCCP2_SET                               0x00000004
      #define CM_PLLA_LOADCCP2_CLR                               0xfffffffb
      #define CM_PLLA_LOADCCP2_MSB                               2
      #define CM_PLLA_LOADCCP2_LSB                               2
      #define CM_PLLA_HOLDDSI0_BITS                              1:1
      #define CM_PLLA_HOLDDSI0_SET                               0x00000002
      #define CM_PLLA_HOLDDSI0_CLR                               0xfffffffd
      #define CM_PLLA_HOLDDSI0_MSB                               1
      #define CM_PLLA_HOLDDSI0_LSB                               1
      #define CM_PLLA_LOADDSI0_BITS                              0:0
      #define CM_PLLA_LOADDSI0_SET                               0x00000001
      #define CM_PLLA_LOADDSI0_CLR                               0xfffffffe
      #define CM_PLLA_LOADDSI0_MSB                               0
      #define CM_PLLA_LOADDSI0_LSB                               0
#define CM_PLLB                                                  HW_REGISTER_RW( 0x7e101170 ) 
   #define CM_PLLB_MASK                                          0x00000303
   #define CM_PLLB_WIDTH                                         10
   #define CM_PLLB_RESET                                         0x00000300
      #define CM_PLLB_DIGRST_BITS                                9:9
      #define CM_PLLB_DIGRST_SET                                 0x00000200
      #define CM_PLLB_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLB_DIGRST_MSB                                 9
      #define CM_PLLB_DIGRST_LSB                                 9
      #define CM_PLLB_ANARST_BITS                                8:8
      #define CM_PLLB_ANARST_SET                                 0x00000100
      #define CM_PLLB_ANARST_CLR                                 0xfffffeff
      #define CM_PLLB_ANARST_MSB                                 8
      #define CM_PLLB_ANARST_LSB                                 8
      #define CM_PLLB_HOLDARM_BITS                               1:1
      #define CM_PLLB_HOLDARM_SET                                0x00000002
      #define CM_PLLB_HOLDARM_CLR                                0xfffffffd
      #define CM_PLLB_HOLDARM_MSB                                1
      #define CM_PLLB_HOLDARM_LSB                                1
      #define CM_PLLB_LOADARM_BITS                               0:0
      #define CM_PLLB_LOADARM_SET                                0x00000001
      #define CM_PLLB_LOADARM_CLR                                0xfffffffe
      #define CM_PLLB_LOADARM_MSB                                0
      #define CM_PLLB_LOADARM_LSB                                0
#define CM_PLLC                                                  HW_REGISTER_RW( 0x7e101108 ) 
   #define CM_PLLC_MASK                                          0x000003ff
   #define CM_PLLC_WIDTH                                         10
   #define CM_PLLC_RESET                                         0x00000300
      #define CM_PLLC_DIGRST_BITS                                9:9
      #define CM_PLLC_DIGRST_SET                                 0x00000200
      #define CM_PLLC_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLC_DIGRST_MSB                                 9
      #define CM_PLLC_DIGRST_LSB                                 9
      #define CM_PLLC_ANARST_BITS                                8:8
      #define CM_PLLC_ANARST_SET                                 0x00000100
      #define CM_PLLC_ANARST_CLR                                 0xfffffeff
      #define CM_PLLC_ANARST_MSB                                 8
      #define CM_PLLC_ANARST_LSB                                 8
      #define CM_PLLC_HOLDPER_BITS                               7:7
      #define CM_PLLC_HOLDPER_SET                                0x00000080
      #define CM_PLLC_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLC_HOLDPER_MSB                                7
      #define CM_PLLC_HOLDPER_LSB                                7
      #define CM_PLLC_LOADPER_BITS                               6:6
      #define CM_PLLC_LOADPER_SET                                0x00000040
      #define CM_PLLC_LOADPER_CLR                                0xffffffbf
      #define CM_PLLC_LOADPER_MSB                                6
      #define CM_PLLC_LOADPER_LSB                                6
      #define CM_PLLC_HOLDCORE2_BITS                             5:5
      #define CM_PLLC_HOLDCORE2_SET                              0x00000020
      #define CM_PLLC_HOLDCORE2_CLR                              0xffffffdf
      #define CM_PLLC_HOLDCORE2_MSB                              5
      #define CM_PLLC_HOLDCORE2_LSB                              5
      #define CM_PLLC_LOADCORE2_BITS                             4:4
      #define CM_PLLC_LOADCORE2_SET                              0x00000010
      #define CM_PLLC_LOADCORE2_CLR                              0xffffffef
      #define CM_PLLC_LOADCORE2_MSB                              4
      #define CM_PLLC_LOADCORE2_LSB                              4
      #define CM_PLLC_HOLDCORE1_BITS                             3:3
      #define CM_PLLC_HOLDCORE1_SET                              0x00000008
      #define CM_PLLC_HOLDCORE1_CLR                              0xfffffff7
      #define CM_PLLC_HOLDCORE1_MSB                              3
      #define CM_PLLC_HOLDCORE1_LSB                              3
      #define CM_PLLC_LOADCORE1_BITS                             2:2
      #define CM_PLLC_LOADCORE1_SET                              0x00000004
      #define CM_PLLC_LOADCORE1_CLR                              0xfffffffb
      #define CM_PLLC_LOADCORE1_MSB                              2
      #define CM_PLLC_LOADCORE1_LSB                              2
      #define CM_PLLC_HOLDCORE0_BITS                             1:1
      #define CM_PLLC_HOLDCORE0_SET                              0x00000002
      #define CM_PLLC_HOLDCORE0_CLR                              0xfffffffd
      #define CM_PLLC_HOLDCORE0_MSB                              1
      #define CM_PLLC_HOLDCORE0_LSB                              1
      #define CM_PLLC_LOADCORE0_BITS                             0:0
      #define CM_PLLC_LOADCORE0_SET                              0x00000001
      #define CM_PLLC_LOADCORE0_CLR                              0xfffffffe
      #define CM_PLLC_LOADCORE0_MSB                              0
      #define CM_PLLC_LOADCORE0_LSB                              0
#define CM_PLLD                                                  HW_REGISTER_RW( 0x7e10110c ) 
   #define CM_PLLD_MASK                                          0x000003ff
   #define CM_PLLD_WIDTH                                         10
   #define CM_PLLD_RESET                                         0x00000300
      #define CM_PLLD_DIGRST_BITS                                9:9
      #define CM_PLLD_DIGRST_SET                                 0x00000200
      #define CM_PLLD_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLD_DIGRST_MSB                                 9
      #define CM_PLLD_DIGRST_LSB                                 9
      #define CM_PLLD_ANARST_BITS                                8:8
      #define CM_PLLD_ANARST_SET                                 0x00000100
      #define CM_PLLD_ANARST_CLR                                 0xfffffeff
      #define CM_PLLD_ANARST_MSB                                 8
      #define CM_PLLD_ANARST_LSB                                 8
      #define CM_PLLD_HOLDPER_BITS                               7:7
      #define CM_PLLD_HOLDPER_SET                                0x00000080
      #define CM_PLLD_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLD_HOLDPER_MSB                                7
      #define CM_PLLD_HOLDPER_LSB                                7
      #define CM_PLLD_LOADPER_BITS                               6:6
      #define CM_PLLD_LOADPER_SET                                0x00000040
      #define CM_PLLD_LOADPER_CLR                                0xffffffbf
      #define CM_PLLD_LOADPER_MSB                                6
      #define CM_PLLD_LOADPER_LSB                                6
      #define CM_PLLD_HOLDCORE_BITS                              5:5
      #define CM_PLLD_HOLDCORE_SET                               0x00000020
      #define CM_PLLD_HOLDCORE_CLR                               0xffffffdf
      #define CM_PLLD_HOLDCORE_MSB                               5
      #define CM_PLLD_HOLDCORE_LSB                               5
      #define CM_PLLD_LOADCORE_BITS                              4:4
      #define CM_PLLD_LOADCORE_SET                               0x00000010
      #define CM_PLLD_LOADCORE_CLR                               0xffffffef
      #define CM_PLLD_LOADCORE_MSB                               4
      #define CM_PLLD_LOADCORE_LSB                               4
      #define CM_PLLD_HOLDDSI1_BITS                              3:3
      #define CM_PLLD_HOLDDSI1_SET                               0x00000008
      #define CM_PLLD_HOLDDSI1_CLR                               0xfffffff7
      #define CM_PLLD_HOLDDSI1_MSB                               3
      #define CM_PLLD_HOLDDSI1_LSB                               3
      #define CM_PLLD_LOADDSI1_BITS                              2:2
      #define CM_PLLD_LOADDSI1_SET                               0x00000004
      #define CM_PLLD_LOADDSI1_CLR                               0xfffffffb
      #define CM_PLLD_LOADDSI1_MSB                               2
      #define CM_PLLD_LOADDSI1_LSB                               2
      #define CM_PLLD_HOLDDSI0_BITS                              1:1
      #define CM_PLLD_HOLDDSI0_SET                               0x00000002
      #define CM_PLLD_HOLDDSI0_CLR                               0xfffffffd
      #define CM_PLLD_HOLDDSI0_MSB                               1
      #define CM_PLLD_HOLDDSI0_LSB                               1
      #define CM_PLLD_LOADDSI0_BITS                              0:0
      #define CM_PLLD_LOADDSI0_SET                               0x00000001
      #define CM_PLLD_LOADDSI0_CLR                               0xfffffffe
      #define CM_PLLD_LOADDSI0_MSB                               0
      #define CM_PLLD_LOADDSI0_LSB                               0
#define CM_PLLH                                                  HW_REGISTER_RW( 0x7e101110 ) 
   #define CM_PLLH_MASK                                          0x00000307
   #define CM_PLLH_WIDTH                                         10
   #define CM_PLLH_RESET                                         0x00000300
      #define CM_PLLH_DIGRST_BITS                                9:9
      #define CM_PLLH_DIGRST_SET                                 0x00000200
      #define CM_PLLH_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLH_DIGRST_MSB                                 9
      #define CM_PLLH_DIGRST_LSB                                 9
      #define CM_PLLH_ANARST_BITS                                8:8
      #define CM_PLLH_ANARST_SET                                 0x00000100
      #define CM_PLLH_ANARST_CLR                                 0xfffffeff
      #define CM_PLLH_ANARST_MSB                                 8
      #define CM_PLLH_ANARST_LSB                                 8
      #define CM_PLLH_LOADRCAL_BITS                              2:2
      #define CM_PLLH_LOADRCAL_SET                               0x00000004
      #define CM_PLLH_LOADRCAL_CLR                               0xfffffffb
      #define CM_PLLH_LOADRCAL_MSB                               2
      #define CM_PLLH_LOADRCAL_LSB                               2
      #define CM_PLLH_LOADAUX_BITS                               1:1
      #define CM_PLLH_LOADAUX_SET                                0x00000002
      #define CM_PLLH_LOADAUX_CLR                                0xfffffffd
      #define CM_PLLH_LOADAUX_MSB                                1
      #define CM_PLLH_LOADAUX_LSB                                1
      #define CM_PLLH_LOADPIX_BITS                               0:0
      #define CM_PLLH_LOADPIX_SET                                0x00000001
      #define CM_PLLH_LOADPIX_CLR                                0xfffffffe
      #define CM_PLLH_LOADPIX_MSB                                0
      #define CM_PLLH_LOADPIX_LSB                                0
#define CM_LOCK                                                  HW_REGISTER_RW( 0x7e101114 ) 
   #define CM_LOCK_MASK                                          0x00001f1f
   #define CM_LOCK_WIDTH                                         13
   #define CM_LOCK_RESET                                         0000000000
      #define CM_LOCK_FLOCKH_BITS                                12:12
      #define CM_LOCK_FLOCKH_SET                                 0x00001000
      #define CM_LOCK_FLOCKH_CLR                                 0xffffefff
      #define CM_LOCK_FLOCKH_MSB                                 12
      #define CM_LOCK_FLOCKH_LSB                                 12
      #define CM_LOCK_FLOCKD_BITS                                11:11
      #define CM_LOCK_FLOCKD_SET                                 0x00000800
      #define CM_LOCK_FLOCKD_CLR                                 0xfffff7ff
      #define CM_LOCK_FLOCKD_MSB                                 11
      #define CM_LOCK_FLOCKD_LSB                                 11
      #define CM_LOCK_FLOCKC_BITS                                10:10
      #define CM_LOCK_FLOCKC_SET                                 0x00000400
      #define CM_LOCK_FLOCKC_CLR                                 0xfffffbff
      #define CM_LOCK_FLOCKC_MSB                                 10
      #define CM_LOCK_FLOCKC_LSB                                 10
      #define CM_LOCK_FLOCKB_BITS                                9:9
      #define CM_LOCK_FLOCKB_SET                                 0x00000200
      #define CM_LOCK_FLOCKB_CLR                                 0xfffffdff
      #define CM_LOCK_FLOCKB_MSB                                 9
      #define CM_LOCK_FLOCKB_LSB                                 9
      #define CM_LOCK_FLOCKA_BITS                                8:8
      #define CM_LOCK_FLOCKA_SET                                 0x00000100
      #define CM_LOCK_FLOCKA_CLR                                 0xfffffeff
      #define CM_LOCK_FLOCKA_MSB                                 8
      #define CM_LOCK_FLOCKA_LSB                                 8
      #define CM_LOCK_LOCKH_BITS                                 4:4
      #define CM_LOCK_LOCKH_SET                                  0x00000010
      #define CM_LOCK_LOCKH_CLR                                  0xffffffef
      #define CM_LOCK_LOCKH_MSB                                  4
      #define CM_LOCK_LOCKH_LSB                                  4
      #define CM_LOCK_LOCKD_BITS                                 3:3
      #define CM_LOCK_LOCKD_SET                                  0x00000008
      #define CM_LOCK_LOCKD_CLR                                  0xfffffff7
      #define CM_LOCK_LOCKD_MSB                                  3
      #define CM_LOCK_LOCKD_LSB                                  3
      #define CM_LOCK_LOCKC_BITS                                 2:2
      #define CM_LOCK_LOCKC_SET                                  0x00000004
      #define CM_LOCK_LOCKC_CLR                                  0xfffffffb
      #define CM_LOCK_LOCKC_MSB                                  2
      #define CM_LOCK_LOCKC_LSB                                  2
      #define CM_LOCK_LOCKB_BITS                                 1:1
      #define CM_LOCK_LOCKB_SET                                  0x00000002
      #define CM_LOCK_LOCKB_CLR                                  0xfffffffd
      #define CM_LOCK_LOCKB_MSB                                  1
      #define CM_LOCK_LOCKB_LSB                                  1
      #define CM_LOCK_LOCKA_BITS                                 0:0
      #define CM_LOCK_LOCKA_SET                                  0x00000001
      #define CM_LOCK_LOCKA_CLR                                  0xfffffffe
      #define CM_LOCK_LOCKA_MSB                                  0
      #define CM_LOCK_LOCKA_LSB                                  0
#define CM_EVENT                                                 HW_REGISTER_RW( 0x7e101118 ) 
   #define CM_EVENT_MASK                                         0x00ffffff
   #define CM_EVENT_WIDTH                                        24
   #define CM_EVENT_RESET                                        0000000000
      #define CM_EVENT_BURSTDONE_BITS                            23:23
      #define CM_EVENT_BURSTDONE_SET                             0x00800000
      #define CM_EVENT_BURSTDONE_CLR                             0xff7fffff
      #define CM_EVENT_BURSTDONE_MSB                             23
      #define CM_EVENT_BURSTDONE_LSB                             23
      #define CM_EVENT_RESUS_BITS                                22:22
      #define CM_EVENT_RESUS_SET                                 0x00400000
      #define CM_EVENT_RESUS_CLR                                 0xffbfffff
      #define CM_EVENT_RESUS_MSB                                 22
      #define CM_EVENT_RESUS_LSB                                 22
      #define CM_EVENT_OCDONE_BITS                               21:21
      #define CM_EVENT_OCDONE_SET                                0x00200000
      #define CM_EVENT_OCDONE_CLR                                0xffdfffff
      #define CM_EVENT_OCDONE_MSB                                21
      #define CM_EVENT_OCDONE_LSB                                21
      #define CM_EVENT_A2WDONE_BITS                              20:20
      #define CM_EVENT_A2WDONE_SET                               0x00100000
      #define CM_EVENT_A2WDONE_CLR                               0xffefffff
      #define CM_EVENT_A2WDONE_MSB                               20
      #define CM_EVENT_A2WDONE_LSB                               20
      #define CM_EVENT_WRFAIL_BITS                               19:19
      #define CM_EVENT_WRFAIL_SET                                0x00080000
      #define CM_EVENT_WRFAIL_CLR                                0xfff7ffff
      #define CM_EVENT_WRFAIL_MSB                                19
      #define CM_EVENT_WRFAIL_LSB                                19
      #define CM_EVENT_BADPASS_BITS                              18:18
      #define CM_EVENT_BADPASS_SET                               0x00040000
      #define CM_EVENT_BADPASS_CLR                               0xfffbffff
      #define CM_EVENT_BADPASS_MSB                               18
      #define CM_EVENT_BADPASS_LSB                               18
      #define CM_EVENT_FLOSSD_BITS                               17:17
      #define CM_EVENT_FLOSSD_SET                                0x00020000
      #define CM_EVENT_FLOSSD_CLR                                0xfffdffff
      #define CM_EVENT_FLOSSD_MSB                                17
      #define CM_EVENT_FLOSSD_LSB                                17
      #define CM_EVENT_FLOSSC_BITS                               16:16
      #define CM_EVENT_FLOSSC_SET                                0x00010000
      #define CM_EVENT_FLOSSC_CLR                                0xfffeffff
      #define CM_EVENT_FLOSSC_MSB                                16
      #define CM_EVENT_FLOSSC_LSB                                16
      #define CM_EVENT_FLOSSB_BITS                               15:15
      #define CM_EVENT_FLOSSB_SET                                0x00008000
      #define CM_EVENT_FLOSSB_CLR                                0xffff7fff
      #define CM_EVENT_FLOSSB_MSB                                15
      #define CM_EVENT_FLOSSB_LSB                                15
      #define CM_EVENT_FLOSSA_BITS                               14:14
      #define CM_EVENT_FLOSSA_SET                                0x00004000
      #define CM_EVENT_FLOSSA_CLR                                0xffffbfff
      #define CM_EVENT_FLOSSA_MSB                                14
      #define CM_EVENT_FLOSSA_LSB                                14
      #define CM_EVENT_FGAIND_BITS                               13:13
      #define CM_EVENT_FGAIND_SET                                0x00002000
      #define CM_EVENT_FGAIND_CLR                                0xffffdfff
      #define CM_EVENT_FGAIND_MSB                                13
      #define CM_EVENT_FGAIND_LSB                                13
      #define CM_EVENT_FGAINC_BITS                               12:12
      #define CM_EVENT_FGAINC_SET                                0x00001000
      #define CM_EVENT_FGAINC_CLR                                0xffffefff
      #define CM_EVENT_FGAINC_MSB                                12
      #define CM_EVENT_FGAINC_LSB                                12
      #define CM_EVENT_FGAINB_BITS                               11:11
      #define CM_EVENT_FGAINB_SET                                0x00000800
      #define CM_EVENT_FGAINB_CLR                                0xfffff7ff
      #define CM_EVENT_FGAINB_MSB                                11
      #define CM_EVENT_FGAINB_LSB                                11
      #define CM_EVENT_FGAINA_BITS                               10:10
      #define CM_EVENT_FGAINA_SET                                0x00000400
      #define CM_EVENT_FGAINA_CLR                                0xfffffbff
      #define CM_EVENT_FGAINA_MSB                                10
      #define CM_EVENT_FGAINA_LSB                                10
      #define CM_EVENT_LOSSH_BITS                                9:9
      #define CM_EVENT_LOSSH_SET                                 0x00000200
      #define CM_EVENT_LOSSH_CLR                                 0xfffffdff
      #define CM_EVENT_LOSSH_MSB                                 9
      #define CM_EVENT_LOSSH_LSB                                 9
      #define CM_EVENT_LOSSD_BITS                                8:8
      #define CM_EVENT_LOSSD_SET                                 0x00000100
      #define CM_EVENT_LOSSD_CLR                                 0xfffffeff
      #define CM_EVENT_LOSSD_MSB                                 8
      #define CM_EVENT_LOSSD_LSB                                 8
      #define CM_EVENT_LOSSC_BITS                                7:7
      #define CM_EVENT_LOSSC_SET                                 0x00000080
      #define CM_EVENT_LOSSC_CLR                                 0xffffff7f
      #define CM_EVENT_LOSSC_MSB                                 7
      #define CM_EVENT_LOSSC_LSB                                 7
      #define CM_EVENT_LOSSB_BITS                                6:6
      #define CM_EVENT_LOSSB_SET                                 0x00000040
      #define CM_EVENT_LOSSB_CLR                                 0xffffffbf
      #define CM_EVENT_LOSSB_MSB                                 6
      #define CM_EVENT_LOSSB_LSB                                 6
      #define CM_EVENT_LOSSA_BITS                                5:5
      #define CM_EVENT_LOSSA_SET                                 0x00000020
      #define CM_EVENT_LOSSA_CLR                                 0xffffffdf
      #define CM_EVENT_LOSSA_MSB                                 5
      #define CM_EVENT_LOSSA_LSB                                 5
      #define CM_EVENT_GAINH_BITS                                4:4
      #define CM_EVENT_GAINH_SET                                 0x00000010
      #define CM_EVENT_GAINH_CLR                                 0xffffffef
      #define CM_EVENT_GAINH_MSB                                 4
      #define CM_EVENT_GAINH_LSB                                 4
      #define CM_EVENT_GAIND_BITS                                3:3
      #define CM_EVENT_GAIND_SET                                 0x00000008
      #define CM_EVENT_GAIND_CLR                                 0xfffffff7
      #define CM_EVENT_GAIND_MSB                                 3
      #define CM_EVENT_GAIND_LSB                                 3
      #define CM_EVENT_GAINC_BITS                                2:2
      #define CM_EVENT_GAINC_SET                                 0x00000004
      #define CM_EVENT_GAINC_CLR                                 0xfffffffb
      #define CM_EVENT_GAINC_MSB                                 2
      #define CM_EVENT_GAINC_LSB                                 2
      #define CM_EVENT_GAINB_BITS                                1:1
      #define CM_EVENT_GAINB_SET                                 0x00000002
      #define CM_EVENT_GAINB_CLR                                 0xfffffffd
      #define CM_EVENT_GAINB_MSB                                 1
      #define CM_EVENT_GAINB_LSB                                 1
      #define CM_EVENT_GAINA_BITS                                0:0
      #define CM_EVENT_GAINA_SET                                 0x00000001
      #define CM_EVENT_GAINA_CLR                                 0xfffffffe
      #define CM_EVENT_GAINA_MSB                                 0
      #define CM_EVENT_GAINA_LSB                                 0
#define CM_INTEN                                                 HW_REGISTER_RW( 0x7e10111c ) 
   #define CM_INTEN_MASK                                         0x00ffffff
   #define CM_INTEN_WIDTH                                        24
   #define CM_INTEN_RESET                                        0000000000
      #define CM_INTEN_BURSTDONE_BITS                            23:23
      #define CM_INTEN_BURSTDONE_SET                             0x00800000
      #define CM_INTEN_BURSTDONE_CLR                             0xff7fffff
      #define CM_INTEN_BURSTDONE_MSB                             23
      #define CM_INTEN_BURSTDONE_LSB                             23
      #define CM_INTEN_RESUS_BITS                                22:22
      #define CM_INTEN_RESUS_SET                                 0x00400000
      #define CM_INTEN_RESUS_CLR                                 0xffbfffff
      #define CM_INTEN_RESUS_MSB                                 22
      #define CM_INTEN_RESUS_LSB                                 22
      #define CM_INTEN_OCDONE_BITS                               21:21
      #define CM_INTEN_OCDONE_SET                                0x00200000
      #define CM_INTEN_OCDONE_CLR                                0xffdfffff
      #define CM_INTEN_OCDONE_MSB                                21
      #define CM_INTEN_OCDONE_LSB                                21
      #define CM_INTEN_A2WDONE_BITS                              20:20
      #define CM_INTEN_A2WDONE_SET                               0x00100000
      #define CM_INTEN_A2WDONE_CLR                               0xffefffff
      #define CM_INTEN_A2WDONE_MSB                               20
      #define CM_INTEN_A2WDONE_LSB                               20
      #define CM_INTEN_WRFAIL_BITS                               19:19
      #define CM_INTEN_WRFAIL_SET                                0x00080000
      #define CM_INTEN_WRFAIL_CLR                                0xfff7ffff
      #define CM_INTEN_WRFAIL_MSB                                19
      #define CM_INTEN_WRFAIL_LSB                                19
      #define CM_INTEN_BADPASS_BITS                              18:18
      #define CM_INTEN_BADPASS_SET                               0x00040000
      #define CM_INTEN_BADPASS_CLR                               0xfffbffff
      #define CM_INTEN_BADPASS_MSB                               18
      #define CM_INTEN_BADPASS_LSB                               18
      #define CM_INTEN_FLOSSD_BITS                               17:17
      #define CM_INTEN_FLOSSD_SET                                0x00020000
      #define CM_INTEN_FLOSSD_CLR                                0xfffdffff
      #define CM_INTEN_FLOSSD_MSB                                17
      #define CM_INTEN_FLOSSD_LSB                                17
      #define CM_INTEN_FLOSSC_BITS                               16:16
      #define CM_INTEN_FLOSSC_SET                                0x00010000
      #define CM_INTEN_FLOSSC_CLR                                0xfffeffff
      #define CM_INTEN_FLOSSC_MSB                                16
      #define CM_INTEN_FLOSSC_LSB                                16
      #define CM_INTEN_FLOSSB_BITS                               15:15
      #define CM_INTEN_FLOSSB_SET                                0x00008000
      #define CM_INTEN_FLOSSB_CLR                                0xffff7fff
      #define CM_INTEN_FLOSSB_MSB                                15
      #define CM_INTEN_FLOSSB_LSB                                15
      #define CM_INTEN_FLOSSA_BITS                               14:14
      #define CM_INTEN_FLOSSA_SET                                0x00004000
      #define CM_INTEN_FLOSSA_CLR                                0xffffbfff
      #define CM_INTEN_FLOSSA_MSB                                14
      #define CM_INTEN_FLOSSA_LSB                                14
      #define CM_INTEN_FGAIND_BITS                               13:13
      #define CM_INTEN_FGAIND_SET                                0x00002000
      #define CM_INTEN_FGAIND_CLR                                0xffffdfff
      #define CM_INTEN_FGAIND_MSB                                13
      #define CM_INTEN_FGAIND_LSB                                13
      #define CM_INTEN_FGAINC_BITS                               12:12
      #define CM_INTEN_FGAINC_SET                                0x00001000
      #define CM_INTEN_FGAINC_CLR                                0xffffefff
      #define CM_INTEN_FGAINC_MSB                                12
      #define CM_INTEN_FGAINC_LSB                                12
      #define CM_INTEN_FGAINB_BITS                               11:11
      #define CM_INTEN_FGAINB_SET                                0x00000800
      #define CM_INTEN_FGAINB_CLR                                0xfffff7ff
      #define CM_INTEN_FGAINB_MSB                                11
      #define CM_INTEN_FGAINB_LSB                                11
      #define CM_INTEN_FGAINA_BITS                               10:10
      #define CM_INTEN_FGAINA_SET                                0x00000400
      #define CM_INTEN_FGAINA_CLR                                0xfffffbff
      #define CM_INTEN_FGAINA_MSB                                10
      #define CM_INTEN_FGAINA_LSB                                10
      #define CM_INTEN_LOSSH_BITS                                9:9
      #define CM_INTEN_LOSSH_SET                                 0x00000200
      #define CM_INTEN_LOSSH_CLR                                 0xfffffdff
      #define CM_INTEN_LOSSH_MSB                                 9
      #define CM_INTEN_LOSSH_LSB                                 9
      #define CM_INTEN_LOSSD_BITS                                8:8
      #define CM_INTEN_LOSSD_SET                                 0x00000100
      #define CM_INTEN_LOSSD_CLR                                 0xfffffeff
      #define CM_INTEN_LOSSD_MSB                                 8
      #define CM_INTEN_LOSSD_LSB                                 8
      #define CM_INTEN_LOSSC_BITS                                7:7
      #define CM_INTEN_LOSSC_SET                                 0x00000080
      #define CM_INTEN_LOSSC_CLR                                 0xffffff7f
      #define CM_INTEN_LOSSC_MSB                                 7
      #define CM_INTEN_LOSSC_LSB                                 7
      #define CM_INTEN_LOSSB_BITS                                6:6
      #define CM_INTEN_LOSSB_SET                                 0x00000040
      #define CM_INTEN_LOSSB_CLR                                 0xffffffbf
      #define CM_INTEN_LOSSB_MSB                                 6
      #define CM_INTEN_LOSSB_LSB                                 6
      #define CM_INTEN_LOSSA_BITS                                5:5
      #define CM_INTEN_LOSSA_SET                                 0x00000020
      #define CM_INTEN_LOSSA_CLR                                 0xffffffdf
      #define CM_INTEN_LOSSA_MSB                                 5
      #define CM_INTEN_LOSSA_LSB                                 5
      #define CM_INTEN_GAINH_BITS                                4:4
      #define CM_INTEN_GAINH_SET                                 0x00000010
      #define CM_INTEN_GAINH_CLR                                 0xffffffef
      #define CM_INTEN_GAINH_MSB                                 4
      #define CM_INTEN_GAINH_LSB                                 4
      #define CM_INTEN_GAIND_BITS                                3:3
      #define CM_INTEN_GAIND_SET                                 0x00000008
      #define CM_INTEN_GAIND_CLR                                 0xfffffff7
      #define CM_INTEN_GAIND_MSB                                 3
      #define CM_INTEN_GAIND_LSB                                 3
      #define CM_INTEN_GAINC_BITS                                2:2
      #define CM_INTEN_GAINC_SET                                 0x00000004
      #define CM_INTEN_GAINC_CLR                                 0xfffffffb
      #define CM_INTEN_GAINC_MSB                                 2
      #define CM_INTEN_GAINC_LSB                                 2
      #define CM_INTEN_GAINB_BITS                                1:1
      #define CM_INTEN_GAINB_SET                                 0x00000002
      #define CM_INTEN_GAINB_CLR                                 0xfffffffd
      #define CM_INTEN_GAINB_MSB                                 1
      #define CM_INTEN_GAINB_LSB                                 1
      #define CM_INTEN_GAINA_BITS                                0:0
      #define CM_INTEN_GAINA_SET                                 0x00000001
      #define CM_INTEN_GAINA_CLR                                 0xfffffffe
      #define CM_INTEN_GAINA_MSB                                 0
      #define CM_INTEN_GAINA_LSB                                 0
#define CM_DSI0HSCK                                              HW_REGISTER_RW( 0x7e101120 ) 
   #define CM_DSI0HSCK_MASK                                      0x00000001
   #define CM_DSI0HSCK_WIDTH                                     1
   #define CM_DSI0HSCK_RESET                                     0000000000
      #define CM_DSI0HSCK_SELPLLD_BITS                           0:0
      #define CM_DSI0HSCK_SELPLLD_SET                            0x00000001
      #define CM_DSI0HSCK_SELPLLD_CLR                            0xfffffffe
      #define CM_DSI0HSCK_SELPLLD_MSB                            0
      #define CM_DSI0HSCK_SELPLLD_LSB                            0
#define CM_CKSM                                                  HW_REGISTER_RW( 0x7e101124 ) 
   #define CM_CKSM_MASK                                          0x003fffff
   #define CM_CKSM_WIDTH                                         22
   #define CM_CKSM_RESET                                         0000000000
      #define CM_CKSM_STEP_BITS                                  21:21
      #define CM_CKSM_STEP_SET                                   0x00200000
      #define CM_CKSM_STEP_CLR                                   0xffdfffff
      #define CM_CKSM_STEP_MSB                                   21
      #define CM_CKSM_STEP_LSB                                   21
      #define CM_CKSM_AUTO_BITS                                  20:20
      #define CM_CKSM_AUTO_SET                                   0x00100000
      #define CM_CKSM_AUTO_CLR                                   0xffefffff
      #define CM_CKSM_AUTO_MSB                                   20
      #define CM_CKSM_AUTO_LSB                                   20
      #define CM_CKSM_OSC_BITS                                   19:18
      #define CM_CKSM_OSC_SET                                    0x000c0000
      #define CM_CKSM_OSC_CLR                                    0xfff3ffff
      #define CM_CKSM_OSC_MSB                                    19
      #define CM_CKSM_OSC_LSB                                    18
      #define CM_CKSM_CFG_BITS                                   17:16
      #define CM_CKSM_CFG_SET                                    0x00030000
      #define CM_CKSM_CFG_CLR                                    0xfffcffff
      #define CM_CKSM_CFG_MSB                                    17
      #define CM_CKSM_CFG_LSB                                    16
      #define CM_CKSM_FRCE_BITS                                  15:8
      #define CM_CKSM_FRCE_SET                                   0x0000ff00
      #define CM_CKSM_FRCE_CLR                                   0xffff00ff
      #define CM_CKSM_FRCE_MSB                                   15
      #define CM_CKSM_FRCE_LSB                                   8
      #define CM_CKSM_STATE_BITS                                 7:0
      #define CM_CKSM_STATE_SET                                  0x000000ff
      #define CM_CKSM_STATE_CLR                                  0xffffff00
      #define CM_CKSM_STATE_MSB                                  7
      #define CM_CKSM_STATE_LSB                                  0
#define CM_OSCFREQI                                              HW_REGISTER_RW( 0x7e101128 ) 
   #define CM_OSCFREQI_MASK                                      0x000000ff
   #define CM_OSCFREQI_WIDTH                                     8
   #define CM_OSCFREQI_RESET                                     0000000000
      #define CM_OSCFREQI_INT_BITS                               7:0
      #define CM_OSCFREQI_INT_SET                                0x000000ff
      #define CM_OSCFREQI_INT_CLR                                0xffffff00
      #define CM_OSCFREQI_INT_MSB                                7
      #define CM_OSCFREQI_INT_LSB                                0
#define CM_OSCFREQF                                              HW_REGISTER_RW( 0x7e10112c ) 
   #define CM_OSCFREQF_MASK                                      0x000fffff
   #define CM_OSCFREQF_WIDTH                                     20
   #define CM_OSCFREQF_RESET                                     0000000000
      #define CM_OSCFREQF_FRAC_BITS                              19:0
      #define CM_OSCFREQF_FRAC_SET                               0x000fffff
      #define CM_OSCFREQF_FRAC_CLR                               0xfff00000
      #define CM_OSCFREQF_FRAC_MSB                               19
      #define CM_OSCFREQF_FRAC_LSB                               0
#define CM_PLLTCTL                                               HW_REGISTER_RW( 0x7e101130 ) 
   #define CM_PLLTCTL_MASK                                       0x000000a7
   #define CM_PLLTCTL_WIDTH                                      8
   #define CM_PLLTCTL_RESET                                      0000000000
      #define CM_PLLTCTL_BUSY_BITS                               7:7
      #define CM_PLLTCTL_BUSY_SET                                0x00000080
      #define CM_PLLTCTL_BUSY_CLR                                0xffffff7f
      #define CM_PLLTCTL_BUSY_MSB                                7
      #define CM_PLLTCTL_BUSY_LSB                                7
      #define CM_PLLTCTL_KILL_BITS                               5:5
      #define CM_PLLTCTL_KILL_SET                                0x00000020
      #define CM_PLLTCTL_KILL_CLR                                0xffffffdf
      #define CM_PLLTCTL_KILL_MSB                                5
      #define CM_PLLTCTL_KILL_LSB                                5
      #define CM_PLLTCTL_SRC_BITS                                2:0
      #define CM_PLLTCTL_SRC_SET                                 0x00000007
      #define CM_PLLTCTL_SRC_CLR                                 0xfffffff8
      #define CM_PLLTCTL_SRC_MSB                                 2
      #define CM_PLLTCTL_SRC_LSB                                 0
#define CM_PLLTCNT0                                              HW_REGISTER_RW( 0x7e101134 ) 
   #define CM_PLLTCNT0_MASK                                      0x00ffffff
   #define CM_PLLTCNT0_WIDTH                                     24
   #define CM_PLLTCNT0_RESET                                     0000000000
      #define CM_PLLTCNT0_CNT_BITS                               23:0
      #define CM_PLLTCNT0_CNT_SET                                0x00ffffff
      #define CM_PLLTCNT0_CNT_CLR                                0xff000000
      #define CM_PLLTCNT0_CNT_MSB                                23
      #define CM_PLLTCNT0_CNT_LSB                                0
#define CM_PLLTCNT1                                              HW_REGISTER_RW( 0x7e101138 ) 
   #define CM_PLLTCNT1_MASK                                      0x00ffffff
   #define CM_PLLTCNT1_WIDTH                                     24
   #define CM_PLLTCNT1_RESET                                     0000000000
      #define CM_PLLTCNT1_CNT_BITS                               23:0
      #define CM_PLLTCNT1_CNT_SET                                0x00ffffff
      #define CM_PLLTCNT1_CNT_CLR                                0xff000000
      #define CM_PLLTCNT1_CNT_MSB                                23
      #define CM_PLLTCNT1_CNT_LSB                                0
#define CM_PLLTCNT2                                              HW_REGISTER_RW( 0x7e10113c ) 
   #define CM_PLLTCNT2_MASK                                      0x00ffffff
   #define CM_PLLTCNT2_WIDTH                                     24
   #define CM_PLLTCNT2_RESET                                     0000000000
      #define CM_PLLTCNT2_CNT_BITS                               23:0
      #define CM_PLLTCNT2_CNT_SET                                0x00ffffff
      #define CM_PLLTCNT2_CNT_CLR                                0xff000000
      #define CM_PLLTCNT2_CNT_MSB                                23
      #define CM_PLLTCNT2_CNT_LSB                                0
#define CM_PLLTCNT3                                              HW_REGISTER_RW( 0x7e101140 ) 
   #define CM_PLLTCNT3_MASK                                      0x00ffffff
   #define CM_PLLTCNT3_WIDTH                                     24
   #define CM_PLLTCNT3_RESET                                     0000000000
      #define CM_PLLTCNT3_CNT_BITS                               23:0
      #define CM_PLLTCNT3_CNT_SET                                0x00ffffff
      #define CM_PLLTCNT3_CNT_CLR                                0xff000000
      #define CM_PLLTCNT3_CNT_MSB                                23
      #define CM_PLLTCNT3_CNT_LSB                                0
#define CM_TDCLKEN                                               HW_REGISTER_RW( 0x7e101144 ) 
   #define CM_TDCLKEN_MASK                                       0x00003fff
   #define CM_TDCLKEN_WIDTH                                      14
   #define CM_TDCLKEN_RESET                                      0000000000
      #define CM_TDCLKEN_IMAGETD_BITS                            13:13
      #define CM_TDCLKEN_IMAGETD_SET                             0x00002000
      #define CM_TDCLKEN_IMAGETD_CLR                             0xffffdfff
      #define CM_TDCLKEN_IMAGETD_MSB                             13
      #define CM_TDCLKEN_IMAGETD_LSB                             13
      #define CM_TDCLKEN_SLIMDFT_BITS                            12:12
      #define CM_TDCLKEN_SLIMDFT_SET                             0x00001000
      #define CM_TDCLKEN_SLIMDFT_CLR                             0xffffefff
      #define CM_TDCLKEN_SLIMDFT_MSB                             12
      #define CM_TDCLKEN_SLIMDFT_LSB                             12
      #define CM_TDCLKEN_USBDFT_BITS                             11:11
      #define CM_TDCLKEN_USBDFT_SET                              0x00000800
      #define CM_TDCLKEN_USBDFT_CLR                              0xfffff7ff
      #define CM_TDCLKEN_USBDFT_MSB                              11
      #define CM_TDCLKEN_USBDFT_LSB                              11
      #define CM_TDCLKEN_MPHIRDFT_BITS                           10:10
      #define CM_TDCLKEN_MPHIRDFT_SET                            0x00000400
      #define CM_TDCLKEN_MPHIRDFT_CLR                            0xfffffbff
      #define CM_TDCLKEN_MPHIRDFT_MSB                            10
      #define CM_TDCLKEN_MPHIRDFT_LSB                            10
      #define CM_TDCLKEN_MPHIWDFT_BITS                           9:9
      #define CM_TDCLKEN_MPHIWDFT_SET                            0x00000200
      #define CM_TDCLKEN_MPHIWDFT_CLR                            0xfffffdff
      #define CM_TDCLKEN_MPHIWDFT_MSB                            9
      #define CM_TDCLKEN_MPHIWDFT_LSB                            9
      #define CM_TDCLKEN_HDMIBYP_BITS                            8:8
      #define CM_TDCLKEN_HDMIBYP_SET                             0x00000100
      #define CM_TDCLKEN_HDMIBYP_CLR                             0xfffffeff
      #define CM_TDCLKEN_HDMIBYP_MSB                             8
      #define CM_TDCLKEN_HDMIBYP_LSB                             8
      #define CM_TDCLKEN_PLLDDIV2_BITS                           7:7
      #define CM_TDCLKEN_PLLDDIV2_SET                            0x00000080
      #define CM_TDCLKEN_PLLDDIV2_CLR                            0xffffff7f
      #define CM_TDCLKEN_PLLDDIV2_MSB                            7
      #define CM_TDCLKEN_PLLDDIV2_LSB                            7
      #define CM_TDCLKEN_PLLCDIV2_BITS                           6:6
      #define CM_TDCLKEN_PLLCDIV2_SET                            0x00000040
      #define CM_TDCLKEN_PLLCDIV2_CLR                            0xffffffbf
      #define CM_TDCLKEN_PLLCDIV2_MSB                            6
      #define CM_TDCLKEN_PLLCDIV2_LSB                            6
      #define CM_TDCLKEN_PLLBDIV2_BITS                           5:5
      #define CM_TDCLKEN_PLLBDIV2_SET                            0x00000020
      #define CM_TDCLKEN_PLLBDIV2_CLR                            0xffffffdf
      #define CM_TDCLKEN_PLLBDIV2_MSB                            5
      #define CM_TDCLKEN_PLLBDIV2_LSB                            5
      #define CM_TDCLKEN_PLLADIV2_BITS                           4:4
      #define CM_TDCLKEN_PLLADIV2_SET                            0x00000010
      #define CM_TDCLKEN_PLLADIV2_CLR                            0xffffffef
      #define CM_TDCLKEN_PLLADIV2_MSB                            4
      #define CM_TDCLKEN_PLLADIV2_LSB                            4
      #define CM_TDCLKEN_PLLDBYP_BITS                            3:3
      #define CM_TDCLKEN_PLLDBYP_SET                             0x00000008
      #define CM_TDCLKEN_PLLDBYP_CLR                             0xfffffff7
      #define CM_TDCLKEN_PLLDBYP_MSB                             3
      #define CM_TDCLKEN_PLLDBYP_LSB                             3
      #define CM_TDCLKEN_PLLCBYP_BITS                            2:2
      #define CM_TDCLKEN_PLLCBYP_SET                             0x00000004
      #define CM_TDCLKEN_PLLCBYP_CLR                             0xfffffffb
      #define CM_TDCLKEN_PLLCBYP_MSB                             2
      #define CM_TDCLKEN_PLLCBYP_LSB                             2
      #define CM_TDCLKEN_PLLBBYP_BITS                            1:1
      #define CM_TDCLKEN_PLLBBYP_SET                             0x00000002
      #define CM_TDCLKEN_PLLBBYP_CLR                             0xfffffffd
      #define CM_TDCLKEN_PLLBBYP_MSB                             1
      #define CM_TDCLKEN_PLLBBYP_LSB                             1
      #define CM_TDCLKEN_PLLABYP_BITS                            0:0
      #define CM_TDCLKEN_PLLABYP_SET                             0x00000001
      #define CM_TDCLKEN_PLLABYP_CLR                             0xfffffffe
      #define CM_TDCLKEN_PLLABYP_MSB                             0
      #define CM_TDCLKEN_PLLABYP_LSB                             0
#define CM_BURSTCTL                                              HW_REGISTER_RW( 0x7e101148 ) 
   #define CM_BURSTCTL_MASK                                      0x000000b0
   #define CM_BURSTCTL_WIDTH                                     8
   #define CM_BURSTCTL_RESET                                     0000000000
      #define CM_BURSTCTL_BUSY_BITS                              7:7
      #define CM_BURSTCTL_BUSY_SET                               0x00000080
      #define CM_BURSTCTL_BUSY_CLR                               0xffffff7f
      #define CM_BURSTCTL_BUSY_MSB                               7
      #define CM_BURSTCTL_BUSY_LSB                               7
      #define CM_BURSTCTL_KILL_BITS                              5:5
      #define CM_BURSTCTL_KILL_SET                               0x00000020
      #define CM_BURSTCTL_KILL_CLR                               0xffffffdf
      #define CM_BURSTCTL_KILL_MSB                               5
      #define CM_BURSTCTL_KILL_LSB                               5
      #define CM_BURSTCTL_ENAB_BITS                              4:4
      #define CM_BURSTCTL_ENAB_SET                               0x00000010
      #define CM_BURSTCTL_ENAB_CLR                               0xffffffef
      #define CM_BURSTCTL_ENAB_MSB                               4
      #define CM_BURSTCTL_ENAB_LSB                               4
#define CM_BURSTCNT                                              HW_REGISTER_RW( 0x7e10114c ) 
   #define CM_BURSTCNT_MASK                                      0x00ffffff
   #define CM_BURSTCNT_WIDTH                                     24
   #define CM_BURSTCNT_RESET                                     0000000000
      #define CM_BURSTCNT_CNT_BITS                               23:0
      #define CM_BURSTCNT_CNT_SET                                0x00ffffff
      #define CM_BURSTCNT_CNT_CLR                                0xff000000
      #define CM_BURSTCNT_CNT_MSB                                23
      #define CM_BURSTCNT_CNT_LSB                                0
#define CM_STOPCLK                                               HW_REGISTER_RW( 0x7e101150 ) 
   #define CM_STOPCLK_MASK                                       0x00000001
   #define CM_STOPCLK_WIDTH                                      1
   #define CM_STOPCLK_RESET                                      0000000000
      #define CM_STOPCLK_ALL_BITS                                0:0
      #define CM_STOPCLK_ALL_SET                                 0x00000001
      #define CM_STOPCLK_ALL_CLR                                 0xfffffffe
      #define CM_STOPCLK_ALL_MSB                                 0
      #define CM_STOPCLK_ALL_LSB                                 0

#else

// This file was generated by the create_regs script
#define CM_PASSWORD                                              0x5a000000
#define CM_BASE                                                  0x7e101000
#define CM_APB_ID                                                0x0000636d
#define CM_GNRICCTL                                              HW_REGISTER_RW( 0x7e101000 ) 
   #define CM_GNRICCTL_MASK                                      0x000fffff
   #define CM_GNRICCTL_WIDTH                                     20
   #define CM_GNRICCTL_RESET                                     0000000000
      #define CM_GNRICCTL_MASH_BITS                              10:9
      #define CM_GNRICCTL_MASH_SET                               0x00000600
      #define CM_GNRICCTL_MASH_CLR                               0xfffff9ff
      #define CM_GNRICCTL_MASH_MSB                               10
      #define CM_GNRICCTL_MASH_LSB                               9
      #define CM_GNRICCTL_FLIP_BITS                              8:8
      #define CM_GNRICCTL_FLIP_SET                               0x00000100
      #define CM_GNRICCTL_FLIP_CLR                               0xfffffeff
      #define CM_GNRICCTL_FLIP_MSB                               8
      #define CM_GNRICCTL_FLIP_LSB                               8
      #define CM_GNRICCTL_BUSY_BITS                              7:7
      #define CM_GNRICCTL_BUSY_SET                               0x00000080
      #define CM_GNRICCTL_BUSY_CLR                               0xffffff7f
      #define CM_GNRICCTL_BUSY_MSB                               7
      #define CM_GNRICCTL_BUSY_LSB                               7
      #define CM_GNRICCTL_GATE_BITS                              6:6
      #define CM_GNRICCTL_GATE_SET                               0x00000040
      #define CM_GNRICCTL_GATE_CLR                               0xffffffbf
      #define CM_GNRICCTL_GATE_MSB                               6
      #define CM_GNRICCTL_GATE_LSB                               6
      #define CM_GNRICCTL_KILL_BITS                              5:5
      #define CM_GNRICCTL_KILL_SET                               0x00000020
      #define CM_GNRICCTL_KILL_CLR                               0xffffffdf
      #define CM_GNRICCTL_KILL_MSB                               5
      #define CM_GNRICCTL_KILL_LSB                               5
      #define CM_GNRICCTL_ENAB_BITS                              4:4
      #define CM_GNRICCTL_ENAB_SET                               0x00000010
      #define CM_GNRICCTL_ENAB_CLR                               0xffffffef
      #define CM_GNRICCTL_ENAB_MSB                               4
      #define CM_GNRICCTL_ENAB_LSB                               4
      #define CM_GNRICCTL_SRC_BITS                               3:0
      #define CM_GNRICCTL_SRC_SET                                0x0000000f
      #define CM_GNRICCTL_SRC_CLR                                0xfffffff0
      #define CM_GNRICCTL_SRC_MSB                                3
      #define CM_GNRICCTL_SRC_LSB                                0
#define CM_GNRICDIV                                              HW_REGISTER_RW( 0x7e101004 ) 
   #define CM_GNRICDIV_MASK                                      0x00ffffff
   #define CM_GNRICDIV_WIDTH                                     24
   #define CM_GNRICDIV_RESET                                     0000000000
      #define CM_GNRICDIV_DIV_BITS                               23:0
      #define CM_GNRICDIV_DIV_SET                                0x00ffffff
      #define CM_GNRICDIV_DIV_CLR                                0xff000000
      #define CM_GNRICDIV_DIV_MSB                                23
      #define CM_GNRICDIV_DIV_LSB                                0
#define CM_VPUCTL                                                HW_REGISTER_RW( 0x7e101008 ) 
   #define CM_VPUCTL_MASK                                        0x000000cf
   #define CM_VPUCTL_WIDTH                                       8
   #define CM_VPUCTL_RESET                                       0x00000041
      #define CM_VPUCTL_BUSY_BITS                                7:7
      #define CM_VPUCTL_BUSY_SET                                 0x00000080
      #define CM_VPUCTL_BUSY_CLR                                 0xffffff7f
      #define CM_VPUCTL_BUSY_MSB                                 7
      #define CM_VPUCTL_BUSY_LSB                                 7
      #define CM_VPUCTL_GATE_BITS                                6:6
      #define CM_VPUCTL_GATE_SET                                 0x00000040
      #define CM_VPUCTL_GATE_CLR                                 0xffffffbf
      #define CM_VPUCTL_GATE_MSB                                 6
      #define CM_VPUCTL_GATE_LSB                                 6
      #define CM_VPUCTL_SRC_BITS                                 3:0
      #define CM_VPUCTL_SRC_SET                                  0x0000000f
      #define CM_VPUCTL_SRC_CLR                                  0xfffffff0
      #define CM_VPUCTL_SRC_MSB                                  3
      #define CM_VPUCTL_SRC_LSB                                  0
#define CM_VPUDIV                                                HW_REGISTER_RW( 0x7e10100c ) 
   #define CM_VPUDIV_MASK                                        0x00fffff0
   #define CM_VPUDIV_WIDTH                                       24
   #define CM_VPUDIV_RESET                                       0x00001000
      #define CM_VPUDIV_DIV_BITS                                 23:4
      #define CM_VPUDIV_DIV_SET                                  0x00fffff0
      #define CM_VPUDIV_DIV_CLR                                  0xff00000f
      #define CM_VPUDIV_DIV_MSB                                  23
      #define CM_VPUDIV_DIV_LSB                                  4
#define CM_SYSCTL                                                HW_REGISTER_RW( 0x7e101010 ) 
   #define CM_SYSCTL_MASK                                        0x00000040
   #define CM_SYSCTL_WIDTH                                       7
   #define CM_SYSCTL_RESET                                       0x00000040
      #define CM_SYSCTL_GATE_BITS                                6:6
      #define CM_SYSCTL_GATE_SET                                 0x00000040
      #define CM_SYSCTL_GATE_CLR                                 0xffffffbf
      #define CM_SYSCTL_GATE_MSB                                 6
      #define CM_SYSCTL_GATE_LSB                                 6
#define CM_SYSDIV                                                HW_REGISTER_RO( 0x7e101014 ) 
   #define CM_SYSDIV_MASK                                        0x00001000
   #define CM_SYSDIV_WIDTH                                       13
   #define CM_SYSDIV_RESET                                       0x00001000
      #define CM_SYSDIV_DIV_BITS                                 12:12
      #define CM_SYSDIV_DIV_SET                                  0x00001000
      #define CM_SYSDIV_DIV_CLR                                  0xffffefff
      #define CM_SYSDIV_DIV_MSB                                  12
      #define CM_SYSDIV_DIV_LSB                                  12
#define CM_PERIACTL                                              HW_REGISTER_RW( 0x7e101018 ) 
   #define CM_PERIACTL_MASK                                      0x00000040
   #define CM_PERIACTL_WIDTH                                     7
   #define CM_PERIACTL_RESET                                     0x00000040
      #define CM_PERIACTL_GATE_BITS                              6:6
      #define CM_PERIACTL_GATE_SET                               0x00000040
      #define CM_PERIACTL_GATE_CLR                               0xffffffbf
      #define CM_PERIACTL_GATE_MSB                               6
      #define CM_PERIACTL_GATE_LSB                               6
#define CM_PERIADIV                                              HW_REGISTER_RO( 0x7e10101c ) 
   #define CM_PERIADIV_MASK                                      0x00001000
   #define CM_PERIADIV_WIDTH                                     13
   #define CM_PERIADIV_RESET                                     0x00001000
      #define CM_PERIADIV_DIV_BITS                               12:12
      #define CM_PERIADIV_DIV_SET                                0x00001000
      #define CM_PERIADIV_DIV_CLR                                0xffffefff
      #define CM_PERIADIV_DIV_MSB                                12
      #define CM_PERIADIV_DIV_LSB                                12
#define CM_PERIICTL                                              HW_REGISTER_RW( 0x7e101020 ) 
   #define CM_PERIICTL_MASK                                      0x00000040
   #define CM_PERIICTL_WIDTH                                     7
   #define CM_PERIICTL_RESET                                     0000000000
      #define CM_PERIICTL_GATE_BITS                              6:6
      #define CM_PERIICTL_GATE_SET                               0x00000040
      #define CM_PERIICTL_GATE_CLR                               0xffffffbf
      #define CM_PERIICTL_GATE_MSB                               6
      #define CM_PERIICTL_GATE_LSB                               6
#define CM_PERIIDIV                                              HW_REGISTER_RO( 0x7e101024 ) 
   #define CM_PERIIDIV_MASK                                      0x00001000
   #define CM_PERIIDIV_WIDTH                                     13
   #define CM_PERIIDIV_RESET                                     0x00001000
      #define CM_PERIIDIV_DIV_BITS                               12:12
      #define CM_PERIIDIV_DIV_SET                                0x00001000
      #define CM_PERIIDIV_DIV_CLR                                0xffffefff
      #define CM_PERIIDIV_DIV_MSB                                12
      #define CM_PERIIDIV_DIV_LSB                                12
#define CM_H264CTL                                               HW_REGISTER_RW( 0x7e101028 ) 
   #define CM_H264CTL_MASK                                       0x000000ff
   #define CM_H264CTL_WIDTH                                      8
   #define CM_H264CTL_RESET                                      0x00000040
      #define CM_H264CTL_BUSY_BITS                               7:7
      #define CM_H264CTL_BUSY_SET                                0x00000080
      #define CM_H264CTL_BUSY_CLR                                0xffffff7f
      #define CM_H264CTL_BUSY_MSB                                7
      #define CM_H264CTL_BUSY_LSB                                7
      #define CM_H264CTL_GATE_BITS                               6:6
      #define CM_H264CTL_GATE_SET                                0x00000040
      #define CM_H264CTL_GATE_CLR                                0xffffffbf
      #define CM_H264CTL_GATE_MSB                                6
      #define CM_H264CTL_GATE_LSB                                6
      #define CM_H264CTL_KILL_BITS                               5:5
      #define CM_H264CTL_KILL_SET                                0x00000020
      #define CM_H264CTL_KILL_CLR                                0xffffffdf
      #define CM_H264CTL_KILL_MSB                                5
      #define CM_H264CTL_KILL_LSB                                5
      #define CM_H264CTL_ENAB_BITS                               4:4
      #define CM_H264CTL_ENAB_SET                                0x00000010
      #define CM_H264CTL_ENAB_CLR                                0xffffffef
      #define CM_H264CTL_ENAB_MSB                                4
      #define CM_H264CTL_ENAB_LSB                                4
      #define CM_H264CTL_SRC_BITS                                3:0
      #define CM_H264CTL_SRC_SET                                 0x0000000f
      #define CM_H264CTL_SRC_CLR                                 0xfffffff0
      #define CM_H264CTL_SRC_MSB                                 3
      #define CM_H264CTL_SRC_LSB                                 0
#define CM_H264DIV                                               HW_REGISTER_RW( 0x7e10102c ) 
   #define CM_H264DIV_MASK                                       0x0000fff0
   #define CM_H264DIV_WIDTH                                      16
   #define CM_H264DIV_RESET                                      0000000000
      #define CM_H264DIV_DIV_BITS                                15:4
      #define CM_H264DIV_DIV_SET                                 0x0000fff0
      #define CM_H264DIV_DIV_CLR                                 0xffff000f
      #define CM_H264DIV_DIV_MSB                                 15
      #define CM_H264DIV_DIV_LSB                                 4
#define CM_ISPCTL                                                HW_REGISTER_RW( 0x7e101030 ) 
   #define CM_ISPCTL_MASK                                        0x000000ff
   #define CM_ISPCTL_WIDTH                                       8
   #define CM_ISPCTL_RESET                                       0x00000040
      #define CM_ISPCTL_BUSY_BITS                                7:7
      #define CM_ISPCTL_BUSY_SET                                 0x00000080
      #define CM_ISPCTL_BUSY_CLR                                 0xffffff7f
      #define CM_ISPCTL_BUSY_MSB                                 7
      #define CM_ISPCTL_BUSY_LSB                                 7
      #define CM_ISPCTL_GATE_BITS                                6:6
      #define CM_ISPCTL_GATE_SET                                 0x00000040
      #define CM_ISPCTL_GATE_CLR                                 0xffffffbf
      #define CM_ISPCTL_GATE_MSB                                 6
      #define CM_ISPCTL_GATE_LSB                                 6
      #define CM_ISPCTL_KILL_BITS                                5:5
      #define CM_ISPCTL_KILL_SET                                 0x00000020
      #define CM_ISPCTL_KILL_CLR                                 0xffffffdf
      #define CM_ISPCTL_KILL_MSB                                 5
      #define CM_ISPCTL_KILL_LSB                                 5
      #define CM_ISPCTL_ENAB_BITS                                4:4
      #define CM_ISPCTL_ENAB_SET                                 0x00000010
      #define CM_ISPCTL_ENAB_CLR                                 0xffffffef
      #define CM_ISPCTL_ENAB_MSB                                 4
      #define CM_ISPCTL_ENAB_LSB                                 4
      #define CM_ISPCTL_SRC_BITS                                 3:0
      #define CM_ISPCTL_SRC_SET                                  0x0000000f
      #define CM_ISPCTL_SRC_CLR                                  0xfffffff0
      #define CM_ISPCTL_SRC_MSB                                  3
      #define CM_ISPCTL_SRC_LSB                                  0
#define CM_ISPDIV                                                HW_REGISTER_RW( 0x7e101034 ) 
   #define CM_ISPDIV_MASK                                        0x0000fff0
   #define CM_ISPDIV_WIDTH                                       16
   #define CM_ISPDIV_RESET                                       0000000000
      #define CM_ISPDIV_DIV_BITS                                 15:4
      #define CM_ISPDIV_DIV_SET                                  0x0000fff0
      #define CM_ISPDIV_DIV_CLR                                  0xffff000f
      #define CM_ISPDIV_DIV_MSB                                  15
      #define CM_ISPDIV_DIV_LSB                                  4
#define CM_ARMCTL                                                HW_REGISTER_RW( 0x7e1011b0 ) 
   #define CM_ARMCTL_MASK                                        0x000011b3
   #define CM_ARMCTL_WIDTH                                       13
   #define CM_ARMCTL_RESET                                       0000000000
      #define CM_ARMCTL_AXIHALF_BITS                             12:12
      #define CM_ARMCTL_AXIHALF_SET                              0x00001000
      #define CM_ARMCTL_AXIHALF_CLR                              0xffffefff
      #define CM_ARMCTL_AXIHALF_MSB                              12
      #define CM_ARMCTL_AXIHALF_LSB                              12
      #define CM_ARMCTL_FLIP_BITS                                8:8
      #define CM_ARMCTL_FLIP_SET                                 0x00000100
      #define CM_ARMCTL_FLIP_CLR                                 0xfffffeff
      #define CM_ARMCTL_FLIP_MSB                                 8
      #define CM_ARMCTL_FLIP_LSB                                 8
      #define CM_ARMCTL_BUSY_BITS                                7:7
      #define CM_ARMCTL_BUSY_SET                                 0x00000080
      #define CM_ARMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_ARMCTL_BUSY_MSB                                 7
      #define CM_ARMCTL_BUSY_LSB                                 7
      #define CM_ARMCTL_KILL_BITS                                5:5
      #define CM_ARMCTL_KILL_SET                                 0x00000020
      #define CM_ARMCTL_KILL_CLR                                 0xffffffdf
      #define CM_ARMCTL_KILL_MSB                                 5
      #define CM_ARMCTL_KILL_LSB                                 5
      #define CM_ARMCTL_ENAB_BITS                                4:4
      #define CM_ARMCTL_ENAB_SET                                 0x00000010
      #define CM_ARMCTL_ENAB_CLR                                 0xffffffef
      #define CM_ARMCTL_ENAB_MSB                                 4
      #define CM_ARMCTL_ENAB_LSB                                 4
      #define CM_ARMCTL_SRC_BITS                                 1:0
      #define CM_ARMCTL_SRC_SET                                  0x00000003
      #define CM_ARMCTL_SRC_CLR                                  0xfffffffc
      #define CM_ARMCTL_SRC_MSB                                  1
      #define CM_ARMCTL_SRC_LSB                                  0
#define CM_ARMDIV                                                HW_REGISTER_RO( 0x7e1011b4 ) 
   #define CM_ARMDIV_MASK                                        0x00001000
   #define CM_ARMDIV_WIDTH                                       13
   #define CM_ARMDIV_RESET                                       0x00001000
      #define CM_ARMDIV_DIV_BITS                                 12:12
      #define CM_ARMDIV_DIV_SET                                  0x00001000
      #define CM_ARMDIV_DIV_CLR                                  0xffffefff
      #define CM_ARMDIV_DIV_MSB                                  12
      #define CM_ARMDIV_DIV_LSB                                  12
#define CM_SDCCTL                                                HW_REGISTER_RW( 0x7e1011a8 ) 
   #define CM_SDCCTL_MASK                                        0x0003f0bf
   #define CM_SDCCTL_WIDTH                                       18
   #define CM_SDCCTL_RESET                                       0x00004000
      #define CM_SDCCTL_UPDATE_BITS                              17:17
      #define CM_SDCCTL_UPDATE_SET                               0x00020000
      #define CM_SDCCTL_UPDATE_CLR                               0xfffdffff
      #define CM_SDCCTL_UPDATE_MSB                               17
      #define CM_SDCCTL_UPDATE_LSB                               17
      #define CM_SDCCTL_ACCPT_BITS                               16:16
      #define CM_SDCCTL_ACCPT_SET                                0x00010000
      #define CM_SDCCTL_ACCPT_CLR                                0xfffeffff
      #define CM_SDCCTL_ACCPT_MSB                                16
      #define CM_SDCCTL_ACCPT_LSB                                16
      #define CM_SDCCTL_CTRL_BITS                                15:12
      #define CM_SDCCTL_CTRL_SET                                 0x0000f000
      #define CM_SDCCTL_CTRL_CLR                                 0xffff0fff
      #define CM_SDCCTL_CTRL_MSB                                 15
      #define CM_SDCCTL_CTRL_LSB                                 12
      #define CM_SDCCTL_BUSY_BITS                                7:7
      #define CM_SDCCTL_BUSY_SET                                 0x00000080
      #define CM_SDCCTL_BUSY_CLR                                 0xffffff7f
      #define CM_SDCCTL_BUSY_MSB                                 7
      #define CM_SDCCTL_BUSY_LSB                                 7
      #define CM_SDCCTL_KILL_BITS                                5:5
      #define CM_SDCCTL_KILL_SET                                 0x00000020
      #define CM_SDCCTL_KILL_CLR                                 0xffffffdf
      #define CM_SDCCTL_KILL_MSB                                 5
      #define CM_SDCCTL_KILL_LSB                                 5
      #define CM_SDCCTL_ENAB_BITS                                4:4
      #define CM_SDCCTL_ENAB_SET                                 0x00000010
      #define CM_SDCCTL_ENAB_CLR                                 0xffffffef
      #define CM_SDCCTL_ENAB_MSB                                 4
      #define CM_SDCCTL_ENAB_LSB                                 4
      #define CM_SDCCTL_SRC_BITS                                 3:0
      #define CM_SDCCTL_SRC_SET                                  0x0000000f
      #define CM_SDCCTL_SRC_CLR                                  0xfffffff0
      #define CM_SDCCTL_SRC_MSB                                  3
      #define CM_SDCCTL_SRC_LSB                                  0
#define CM_SDCDIV                                                HW_REGISTER_RW( 0x7e1011ac ) 
   #define CM_SDCDIV_MASK                                        0x0003f000
   #define CM_SDCDIV_WIDTH                                       18
   #define CM_SDCDIV_RESET                                       0000000000
      #define CM_SDCDIV_DIV_BITS                                 17:12
      #define CM_SDCDIV_DIV_SET                                  0x0003f000
      #define CM_SDCDIV_DIV_CLR                                  0xfffc0fff
      #define CM_SDCDIV_DIV_MSB                                  17
      #define CM_SDCDIV_DIV_LSB                                  12
#define CM_V3DCTL                                                HW_REGISTER_RW( 0x7e101038 ) 
   #define CM_V3DCTL_MASK                                        0x000000ff
   #define CM_V3DCTL_WIDTH                                       8
   #define CM_V3DCTL_RESET                                       0x00000040
      #define CM_V3DCTL_BUSY_BITS                                7:7
      #define CM_V3DCTL_BUSY_SET                                 0x00000080
      #define CM_V3DCTL_BUSY_CLR                                 0xffffff7f
      #define CM_V3DCTL_BUSY_MSB                                 7
      #define CM_V3DCTL_BUSY_LSB                                 7
      #define CM_V3DCTL_GATE_BITS                                6:6
      #define CM_V3DCTL_GATE_SET                                 0x00000040
      #define CM_V3DCTL_GATE_CLR                                 0xffffffbf
      #define CM_V3DCTL_GATE_MSB                                 6
      #define CM_V3DCTL_GATE_LSB                                 6
      #define CM_V3DCTL_KILL_BITS                                5:5
      #define CM_V3DCTL_KILL_SET                                 0x00000020
      #define CM_V3DCTL_KILL_CLR                                 0xffffffdf
      #define CM_V3DCTL_KILL_MSB                                 5
      #define CM_V3DCTL_KILL_LSB                                 5
      #define CM_V3DCTL_ENAB_BITS                                4:4
      #define CM_V3DCTL_ENAB_SET                                 0x00000010
      #define CM_V3DCTL_ENAB_CLR                                 0xffffffef
      #define CM_V3DCTL_ENAB_MSB                                 4
      #define CM_V3DCTL_ENAB_LSB                                 4
      #define CM_V3DCTL_SRC_BITS                                 3:0
      #define CM_V3DCTL_SRC_SET                                  0x0000000f
      #define CM_V3DCTL_SRC_CLR                                  0xfffffff0
      #define CM_V3DCTL_SRC_MSB                                  3
      #define CM_V3DCTL_SRC_LSB                                  0
#define CM_V3DDIV                                                HW_REGISTER_RW( 0x7e10103c ) 
   #define CM_V3DDIV_MASK                                        0x0000fff0
   #define CM_V3DDIV_WIDTH                                       16
   #define CM_V3DDIV_RESET                                       0000000000
      #define CM_V3DDIV_DIV_BITS                                 15:4
      #define CM_V3DDIV_DIV_SET                                  0x0000fff0
      #define CM_V3DDIV_DIV_CLR                                  0xffff000f
      #define CM_V3DDIV_DIV_MSB                                  15
      #define CM_V3DDIV_DIV_LSB                                  4
#define CM_CAM0CTL                                               HW_REGISTER_RW( 0x7e101040 ) 
   #define CM_CAM0CTL_MASK                                       0x000000bf
   #define CM_CAM0CTL_WIDTH                                      8
   #define CM_CAM0CTL_RESET                                      0000000000
      #define CM_CAM0CTL_BUSY_BITS                               7:7
      #define CM_CAM0CTL_BUSY_SET                                0x00000080
      #define CM_CAM0CTL_BUSY_CLR                                0xffffff7f
      #define CM_CAM0CTL_BUSY_MSB                                7
      #define CM_CAM0CTL_BUSY_LSB                                7
      #define CM_CAM0CTL_KILL_BITS                               5:5
      #define CM_CAM0CTL_KILL_SET                                0x00000020
      #define CM_CAM0CTL_KILL_CLR                                0xffffffdf
      #define CM_CAM0CTL_KILL_MSB                                5
      #define CM_CAM0CTL_KILL_LSB                                5
      #define CM_CAM0CTL_ENAB_BITS                               4:4
      #define CM_CAM0CTL_ENAB_SET                                0x00000010
      #define CM_CAM0CTL_ENAB_CLR                                0xffffffef
      #define CM_CAM0CTL_ENAB_MSB                                4
      #define CM_CAM0CTL_ENAB_LSB                                4
      #define CM_CAM0CTL_SRC_BITS                                3:0
      #define CM_CAM0CTL_SRC_SET                                 0x0000000f
      #define CM_CAM0CTL_SRC_CLR                                 0xfffffff0
      #define CM_CAM0CTL_SRC_MSB                                 3
      #define CM_CAM0CTL_SRC_LSB                                 0
#define CM_CAM0DIV                                               HW_REGISTER_RW( 0x7e101044 ) 
   #define CM_CAM0DIV_MASK                                       0x0000fff0
   #define CM_CAM0DIV_WIDTH                                      16
   #define CM_CAM0DIV_RESET                                      0000000000
      #define CM_CAM0DIV_DIV_BITS                                15:4
      #define CM_CAM0DIV_DIV_SET                                 0x0000fff0
      #define CM_CAM0DIV_DIV_CLR                                 0xffff000f
      #define CM_CAM0DIV_DIV_MSB                                 15
      #define CM_CAM0DIV_DIV_LSB                                 4
#define CM_CAM1CTL                                               HW_REGISTER_RW( 0x7e101048 ) 
   #define CM_CAM1CTL_MASK                                       0x000000bf
   #define CM_CAM1CTL_WIDTH                                      8
   #define CM_CAM1CTL_RESET                                      0000000000
      #define CM_CAM1CTL_BUSY_BITS                               7:7
      #define CM_CAM1CTL_BUSY_SET                                0x00000080
      #define CM_CAM1CTL_BUSY_CLR                                0xffffff7f
      #define CM_CAM1CTL_BUSY_MSB                                7
      #define CM_CAM1CTL_BUSY_LSB                                7
      #define CM_CAM1CTL_KILL_BITS                               5:5
      #define CM_CAM1CTL_KILL_SET                                0x00000020
      #define CM_CAM1CTL_KILL_CLR                                0xffffffdf
      #define CM_CAM1CTL_KILL_MSB                                5
      #define CM_CAM1CTL_KILL_LSB                                5
      #define CM_CAM1CTL_ENAB_BITS                               4:4
      #define CM_CAM1CTL_ENAB_SET                                0x00000010
      #define CM_CAM1CTL_ENAB_CLR                                0xffffffef
      #define CM_CAM1CTL_ENAB_MSB                                4
      #define CM_CAM1CTL_ENAB_LSB                                4
      #define CM_CAM1CTL_SRC_BITS                                3:0
      #define CM_CAM1CTL_SRC_SET                                 0x0000000f
      #define CM_CAM1CTL_SRC_CLR                                 0xfffffff0
      #define CM_CAM1CTL_SRC_MSB                                 3
      #define CM_CAM1CTL_SRC_LSB                                 0
#define CM_CAM1DIV                                               HW_REGISTER_RW( 0x7e10104c ) 
   #define CM_CAM1DIV_MASK                                       0x0000fff0
   #define CM_CAM1DIV_WIDTH                                      16
   #define CM_CAM1DIV_RESET                                      0000000000
      #define CM_CAM1DIV_DIV_BITS                                15:4
      #define CM_CAM1DIV_DIV_SET                                 0x0000fff0
      #define CM_CAM1DIV_DIV_CLR                                 0xffff000f
      #define CM_CAM1DIV_DIV_MSB                                 15
      #define CM_CAM1DIV_DIV_LSB                                 4
#define CM_CCP2CTL                                               HW_REGISTER_RW( 0x7e101050 ) 
   #define CM_CCP2CTL_MASK                                       0x00000017
   #define CM_CCP2CTL_WIDTH                                      5
   #define CM_CCP2CTL_RESET                                      0000000000
      #define CM_CCP2CTL_ENAB_BITS                               4:4
      #define CM_CCP2CTL_ENAB_SET                                0x00000010
      #define CM_CCP2CTL_ENAB_CLR                                0xffffffef
      #define CM_CCP2CTL_ENAB_MSB                                4
      #define CM_CCP2CTL_ENAB_LSB                                4
      #define CM_CCP2CTL_SRC_BITS                                2:0
      #define CM_CCP2CTL_SRC_SET                                 0x00000007
      #define CM_CCP2CTL_SRC_CLR                                 0xfffffff8
      #define CM_CCP2CTL_SRC_MSB                                 2
      #define CM_CCP2CTL_SRC_LSB                                 0
#define CM_DSI0ECTL                                              HW_REGISTER_RW( 0x7e101058 ) 
   #define CM_DSI0ECTL_MASK                                      0x000000bf
   #define CM_DSI0ECTL_WIDTH                                     8
   #define CM_DSI0ECTL_RESET                                     0000000000
      #define CM_DSI0ECTL_BUSY_BITS                              7:7
      #define CM_DSI0ECTL_BUSY_SET                               0x00000080
      #define CM_DSI0ECTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI0ECTL_BUSY_MSB                               7
      #define CM_DSI0ECTL_BUSY_LSB                               7
      #define CM_DSI0ECTL_KILL_BITS                              5:5
      #define CM_DSI0ECTL_KILL_SET                               0x00000020
      #define CM_DSI0ECTL_KILL_CLR                               0xffffffdf
      #define CM_DSI0ECTL_KILL_MSB                               5
      #define CM_DSI0ECTL_KILL_LSB                               5
      #define CM_DSI0ECTL_ENAB_BITS                              4:4
      #define CM_DSI0ECTL_ENAB_SET                               0x00000010
      #define CM_DSI0ECTL_ENAB_CLR                               0xffffffef
      #define CM_DSI0ECTL_ENAB_MSB                               4
      #define CM_DSI0ECTL_ENAB_LSB                               4
      #define CM_DSI0ECTL_SRC_BITS                               3:0
      #define CM_DSI0ECTL_SRC_SET                                0x0000000f
      #define CM_DSI0ECTL_SRC_CLR                                0xfffffff0
      #define CM_DSI0ECTL_SRC_MSB                                3
      #define CM_DSI0ECTL_SRC_LSB                                0
#define CM_DSI0EDIV                                              HW_REGISTER_RW( 0x7e10105c ) 
   #define CM_DSI0EDIV_MASK                                      0x0000fff0
   #define CM_DSI0EDIV_WIDTH                                     16
   #define CM_DSI0EDIV_RESET                                     0000000000
      #define CM_DSI0EDIV_DIV_BITS                               15:4
      #define CM_DSI0EDIV_DIV_SET                                0x0000fff0
      #define CM_DSI0EDIV_DIV_CLR                                0xffff000f
      #define CM_DSI0EDIV_DIV_MSB                                15
      #define CM_DSI0EDIV_DIV_LSB                                4
#define CM_DSI0PCTL                                              HW_REGISTER_RW( 0x7e101060 ) 
   #define CM_DSI0PCTL_MASK                                      0x0000001f
   #define CM_DSI0PCTL_WIDTH                                     5
   #define CM_DSI0PCTL_RESET                                     0000000000
      #define CM_DSI0PCTL_ENAB_BITS                              4:4
      #define CM_DSI0PCTL_ENAB_SET                               0x00000010
      #define CM_DSI0PCTL_ENAB_CLR                               0xffffffef
      #define CM_DSI0PCTL_ENAB_MSB                               4
      #define CM_DSI0PCTL_ENAB_LSB                               4
      #define CM_DSI0PCTL_SRC_BITS                               3:0
      #define CM_DSI0PCTL_SRC_SET                                0x0000000f
      #define CM_DSI0PCTL_SRC_CLR                                0xfffffff0
      #define CM_DSI0PCTL_SRC_MSB                                3
      #define CM_DSI0PCTL_SRC_LSB                                0
#define CM_DSI1ECTL                                              HW_REGISTER_RW( 0x7e101158 ) 
   #define CM_DSI1ECTL_MASK                                      0x000000bf
   #define CM_DSI1ECTL_WIDTH                                     8
   #define CM_DSI1ECTL_RESET                                     0000000000
      #define CM_DSI1ECTL_BUSY_BITS                              7:7
      #define CM_DSI1ECTL_BUSY_SET                               0x00000080
      #define CM_DSI1ECTL_BUSY_CLR                               0xffffff7f
      #define CM_DSI1ECTL_BUSY_MSB                               7
      #define CM_DSI1ECTL_BUSY_LSB                               7
      #define CM_DSI1ECTL_KILL_BITS                              5:5
      #define CM_DSI1ECTL_KILL_SET                               0x00000020
      #define CM_DSI1ECTL_KILL_CLR                               0xffffffdf
      #define CM_DSI1ECTL_KILL_MSB                               5
      #define CM_DSI1ECTL_KILL_LSB                               5
      #define CM_DSI1ECTL_ENAB_BITS                              4:4
      #define CM_DSI1ECTL_ENAB_SET                               0x00000010
      #define CM_DSI1ECTL_ENAB_CLR                               0xffffffef
      #define CM_DSI1ECTL_ENAB_MSB                               4
      #define CM_DSI1ECTL_ENAB_LSB                               4
      #define CM_DSI1ECTL_SRC_BITS                               3:0
      #define CM_DSI1ECTL_SRC_SET                                0x0000000f
      #define CM_DSI1ECTL_SRC_CLR                                0xfffffff0
      #define CM_DSI1ECTL_SRC_MSB                                3
      #define CM_DSI1ECTL_SRC_LSB                                0
#define CM_DSI1EDIV                                              HW_REGISTER_RW( 0x7e10115c ) 
   #define CM_DSI1EDIV_MASK                                      0x0000fff0
   #define CM_DSI1EDIV_WIDTH                                     16
   #define CM_DSI1EDIV_RESET                                     0000000000
      #define CM_DSI1EDIV_DIV_BITS                               15:4
      #define CM_DSI1EDIV_DIV_SET                                0x0000fff0
      #define CM_DSI1EDIV_DIV_CLR                                0xffff000f
      #define CM_DSI1EDIV_DIV_MSB                                15
      #define CM_DSI1EDIV_DIV_LSB                                4
#define CM_DSI1PCTL                                              HW_REGISTER_RW( 0x7e101160 ) 
   #define CM_DSI1PCTL_MASK                                      0x0000001f
   #define CM_DSI1PCTL_WIDTH                                     5
   #define CM_DSI1PCTL_RESET                                     0000000000
      #define CM_DSI1PCTL_ENAB_BITS                              4:4
      #define CM_DSI1PCTL_ENAB_SET                               0x00000010
      #define CM_DSI1PCTL_ENAB_CLR                               0xffffffef
      #define CM_DSI1PCTL_ENAB_MSB                               4
      #define CM_DSI1PCTL_ENAB_LSB                               4
      #define CM_DSI1PCTL_SRC_BITS                               3:0
      #define CM_DSI1PCTL_SRC_SET                                0x0000000f
      #define CM_DSI1PCTL_SRC_CLR                                0xfffffff0
      #define CM_DSI1PCTL_SRC_MSB                                3
      #define CM_DSI1PCTL_SRC_LSB                                0
#define CM_DPICTL                                                HW_REGISTER_RW( 0x7e101068 ) 
   #define CM_DPICTL_MASK                                        0x000000bf
   #define CM_DPICTL_WIDTH                                       8
   #define CM_DPICTL_RESET                                       0000000000
      #define CM_DPICTL_BUSY_BITS                                7:7
      #define CM_DPICTL_BUSY_SET                                 0x00000080
      #define CM_DPICTL_BUSY_CLR                                 0xffffff7f
      #define CM_DPICTL_BUSY_MSB                                 7
      #define CM_DPICTL_BUSY_LSB                                 7
      #define CM_DPICTL_KILL_BITS                                5:5
      #define CM_DPICTL_KILL_SET                                 0x00000020
      #define CM_DPICTL_KILL_CLR                                 0xffffffdf
      #define CM_DPICTL_KILL_MSB                                 5
      #define CM_DPICTL_KILL_LSB                                 5
      #define CM_DPICTL_ENAB_BITS                                4:4
      #define CM_DPICTL_ENAB_SET                                 0x00000010
      #define CM_DPICTL_ENAB_CLR                                 0xffffffef
      #define CM_DPICTL_ENAB_MSB                                 4
      #define CM_DPICTL_ENAB_LSB                                 4
      #define CM_DPICTL_SRC_BITS                                 3:0
      #define CM_DPICTL_SRC_SET                                  0x0000000f
      #define CM_DPICTL_SRC_CLR                                  0xfffffff0
      #define CM_DPICTL_SRC_MSB                                  3
      #define CM_DPICTL_SRC_LSB                                  0
#define CM_DPIDIV                                                HW_REGISTER_RW( 0x7e10106c ) 
   #define CM_DPIDIV_MASK                                        0x0000fff0
   #define CM_DPIDIV_WIDTH                                       16
   #define CM_DPIDIV_RESET                                       0000000000
      #define CM_DPIDIV_DIV_BITS                                 15:4
      #define CM_DPIDIV_DIV_SET                                  0x0000fff0
      #define CM_DPIDIV_DIV_CLR                                  0xffff000f
      #define CM_DPIDIV_DIV_MSB                                  15
      #define CM_DPIDIV_DIV_LSB                                  4
#define CM_DFTCTL                                                HW_REGISTER_RW( 0x7e101168 ) 
   #define CM_DFTCTL_MASK                                        0x000000bf
   #define CM_DFTCTL_WIDTH                                       8
   #define CM_DFTCTL_RESET                                       0000000000
      #define CM_DFTCTL_BUSY_BITS                                7:7
      #define CM_DFTCTL_BUSY_SET                                 0x00000080
      #define CM_DFTCTL_BUSY_CLR                                 0xffffff7f
      #define CM_DFTCTL_BUSY_MSB                                 7
      #define CM_DFTCTL_BUSY_LSB                                 7
      #define CM_DFTCTL_KILL_BITS                                5:5
      #define CM_DFTCTL_KILL_SET                                 0x00000020
      #define CM_DFTCTL_KILL_CLR                                 0xffffffdf
      #define CM_DFTCTL_KILL_MSB                                 5
      #define CM_DFTCTL_KILL_LSB                                 5
      #define CM_DFTCTL_ENAB_BITS                                4:4
      #define CM_DFTCTL_ENAB_SET                                 0x00000010
      #define CM_DFTCTL_ENAB_CLR                                 0xffffffef
      #define CM_DFTCTL_ENAB_MSB                                 4
      #define CM_DFTCTL_ENAB_LSB                                 4
      #define CM_DFTCTL_SRC_BITS                                 3:0
      #define CM_DFTCTL_SRC_SET                                  0x0000000f
      #define CM_DFTCTL_SRC_CLR                                  0xfffffff0
      #define CM_DFTCTL_SRC_MSB                                  3
      #define CM_DFTCTL_SRC_LSB                                  0
#define CM_DFTDIV                                                HW_REGISTER_RW( 0x7e10116c ) 
   #define CM_DFTDIV_MASK                                        0x0001f000
   #define CM_DFTDIV_WIDTH                                       17
   #define CM_DFTDIV_RESET                                       0000000000
      #define CM_DFTDIV_DIV_BITS                                 16:12
      #define CM_DFTDIV_DIV_SET                                  0x0001f000
      #define CM_DFTDIV_DIV_CLR                                  0xfffe0fff
      #define CM_DFTDIV_DIV_MSB                                  16
      #define CM_DFTDIV_DIV_LSB                                  12
#define CM_GP0CTL                                                HW_REGISTER_RW( 0x7e101070 ) 
   #define CM_GP0CTL_MASK                                        0x000006bf
   #define CM_GP0CTL_WIDTH                                       11
   #define CM_GP0CTL_RESET                                       0x00000200
      #define CM_GP0CTL_MASH_BITS                                10:9
      #define CM_GP0CTL_MASH_SET                                 0x00000600
      #define CM_GP0CTL_MASH_CLR                                 0xfffff9ff
      #define CM_GP0CTL_MASH_MSB                                 10
      #define CM_GP0CTL_MASH_LSB                                 9
      #define CM_GP0CTL_BUSY_BITS                                7:7
      #define CM_GP0CTL_BUSY_SET                                 0x00000080
      #define CM_GP0CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP0CTL_BUSY_MSB                                 7
      #define CM_GP0CTL_BUSY_LSB                                 7
      #define CM_GP0CTL_KILL_BITS                                5:5
      #define CM_GP0CTL_KILL_SET                                 0x00000020
      #define CM_GP0CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP0CTL_KILL_MSB                                 5
      #define CM_GP0CTL_KILL_LSB                                 5
      #define CM_GP0CTL_ENAB_BITS                                4:4
      #define CM_GP0CTL_ENAB_SET                                 0x00000010
      #define CM_GP0CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP0CTL_ENAB_MSB                                 4
      #define CM_GP0CTL_ENAB_LSB                                 4
      #define CM_GP0CTL_SRC_BITS                                 3:0
      #define CM_GP0CTL_SRC_SET                                  0x0000000f
      #define CM_GP0CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP0CTL_SRC_MSB                                  3
      #define CM_GP0CTL_SRC_LSB                                  0
#define CM_GP0DIV                                                HW_REGISTER_RW( 0x7e101074 ) 
   #define CM_GP0DIV_MASK                                        0x00ffffff
   #define CM_GP0DIV_WIDTH                                       24
   #define CM_GP0DIV_RESET                                       0000000000
      #define CM_GP0DIV_DIV_BITS                                 23:0
      #define CM_GP0DIV_DIV_SET                                  0x00ffffff
      #define CM_GP0DIV_DIV_CLR                                  0xff000000
      #define CM_GP0DIV_DIV_MSB                                  23
      #define CM_GP0DIV_DIV_LSB                                  0
#define CM_GP1CTL                                                HW_REGISTER_RW( 0x7e101078 ) 
   #define CM_GP1CTL_MASK                                        0x000006bf
   #define CM_GP1CTL_WIDTH                                       11
   #define CM_GP1CTL_RESET                                       0x00000200
      #define CM_GP1CTL_MASH_BITS                                10:9
      #define CM_GP1CTL_MASH_SET                                 0x00000600
      #define CM_GP1CTL_MASH_CLR                                 0xfffff9ff
      #define CM_GP1CTL_MASH_MSB                                 10
      #define CM_GP1CTL_MASH_LSB                                 9
      #define CM_GP1CTL_BUSY_BITS                                7:7
      #define CM_GP1CTL_BUSY_SET                                 0x00000080
      #define CM_GP1CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP1CTL_BUSY_MSB                                 7
      #define CM_GP1CTL_BUSY_LSB                                 7
      #define CM_GP1CTL_KILL_BITS                                5:5
      #define CM_GP1CTL_KILL_SET                                 0x00000020
      #define CM_GP1CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP1CTL_KILL_MSB                                 5
      #define CM_GP1CTL_KILL_LSB                                 5
      #define CM_GP1CTL_ENAB_BITS                                4:4
      #define CM_GP1CTL_ENAB_SET                                 0x00000010
      #define CM_GP1CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP1CTL_ENAB_MSB                                 4
      #define CM_GP1CTL_ENAB_LSB                                 4
      #define CM_GP1CTL_SRC_BITS                                 3:0
      #define CM_GP1CTL_SRC_SET                                  0x0000000f
      #define CM_GP1CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP1CTL_SRC_MSB                                  3
      #define CM_GP1CTL_SRC_LSB                                  0
#define CM_GP1DIV                                                HW_REGISTER_RW( 0x7e10107c ) 
   #define CM_GP1DIV_MASK                                        0x00ffffff
   #define CM_GP1DIV_WIDTH                                       24
   #define CM_GP1DIV_RESET                                       0000000000
      #define CM_GP1DIV_DIV_BITS                                 23:0
      #define CM_GP1DIV_DIV_SET                                  0x00ffffff
      #define CM_GP1DIV_DIV_CLR                                  0xff000000
      #define CM_GP1DIV_DIV_MSB                                  23
      #define CM_GP1DIV_DIV_LSB                                  0
#define CM_GP2CTL                                                HW_REGISTER_RW( 0x7e101080 ) 
   #define CM_GP2CTL_MASK                                        0x000000bf
   #define CM_GP2CTL_WIDTH                                       8
   #define CM_GP2CTL_RESET                                       0000000000
      #define CM_GP2CTL_BUSY_BITS                                7:7
      #define CM_GP2CTL_BUSY_SET                                 0x00000080
      #define CM_GP2CTL_BUSY_CLR                                 0xffffff7f
      #define CM_GP2CTL_BUSY_MSB                                 7
      #define CM_GP2CTL_BUSY_LSB                                 7
      #define CM_GP2CTL_KILL_BITS                                5:5
      #define CM_GP2CTL_KILL_SET                                 0x00000020
      #define CM_GP2CTL_KILL_CLR                                 0xffffffdf
      #define CM_GP2CTL_KILL_MSB                                 5
      #define CM_GP2CTL_KILL_LSB                                 5
      #define CM_GP2CTL_ENAB_BITS                                4:4
      #define CM_GP2CTL_ENAB_SET                                 0x00000010
      #define CM_GP2CTL_ENAB_CLR                                 0xffffffef
      #define CM_GP2CTL_ENAB_MSB                                 4
      #define CM_GP2CTL_ENAB_LSB                                 4
      #define CM_GP2CTL_SRC_BITS                                 3:0
      #define CM_GP2CTL_SRC_SET                                  0x0000000f
      #define CM_GP2CTL_SRC_CLR                                  0xfffffff0
      #define CM_GP2CTL_SRC_MSB                                  3
      #define CM_GP2CTL_SRC_LSB                                  0
#define CM_GP2DIV                                                HW_REGISTER_RW( 0x7e101084 ) 
   #define CM_GP2DIV_MASK                                        0x00ffffff
   #define CM_GP2DIV_WIDTH                                       24
   #define CM_GP2DIV_RESET                                       0000000000
      #define CM_GP2DIV_DIV_BITS                                 23:0
      #define CM_GP2DIV_DIV_SET                                  0x00ffffff
      #define CM_GP2DIV_DIV_CLR                                  0xff000000
      #define CM_GP2DIV_DIV_MSB                                  23
      #define CM_GP2DIV_DIV_LSB                                  0
#define CM_HSMCTL                                                HW_REGISTER_RW( 0x7e101088 ) 
   #define CM_HSMCTL_MASK                                        0x000000ff
   #define CM_HSMCTL_WIDTH                                       8
   #define CM_HSMCTL_RESET                                       0000000000
      #define CM_HSMCTL_BUSY_BITS                                7:7
      #define CM_HSMCTL_BUSY_SET                                 0x00000080
      #define CM_HSMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_HSMCTL_BUSY_MSB                                 7
      #define CM_HSMCTL_BUSY_LSB                                 7
      #define CM_HSMCTL_GATE_BITS                                6:6
      #define CM_HSMCTL_GATE_SET                                 0x00000040
      #define CM_HSMCTL_GATE_CLR                                 0xffffffbf
      #define CM_HSMCTL_GATE_MSB                                 6
      #define CM_HSMCTL_GATE_LSB                                 6
      #define CM_HSMCTL_KILL_BITS                                5:5
      #define CM_HSMCTL_KILL_SET                                 0x00000020
      #define CM_HSMCTL_KILL_CLR                                 0xffffffdf
      #define CM_HSMCTL_KILL_MSB                                 5
      #define CM_HSMCTL_KILL_LSB                                 5
      #define CM_HSMCTL_ENAB_BITS                                4:4
      #define CM_HSMCTL_ENAB_SET                                 0x00000010
      #define CM_HSMCTL_ENAB_CLR                                 0xffffffef
      #define CM_HSMCTL_ENAB_MSB                                 4
      #define CM_HSMCTL_ENAB_LSB                                 4
      #define CM_HSMCTL_SRC_BITS                                 3:0
      #define CM_HSMCTL_SRC_SET                                  0x0000000f
      #define CM_HSMCTL_SRC_CLR                                  0xfffffff0
      #define CM_HSMCTL_SRC_MSB                                  3
      #define CM_HSMCTL_SRC_LSB                                  0
#define CM_HSMDIV                                                HW_REGISTER_RW( 0x7e10108c ) 
   #define CM_HSMDIV_MASK                                        0x0000fff0
   #define CM_HSMDIV_WIDTH                                       16
   #define CM_HSMDIV_RESET                                       0000000000
      #define CM_HSMDIV_DIV_BITS                                 15:4
      #define CM_HSMDIV_DIV_SET                                  0x0000fff0
      #define CM_HSMDIV_DIV_CLR                                  0xffff000f
      #define CM_HSMDIV_DIV_MSB                                  15
      #define CM_HSMDIV_DIV_LSB                                  4
#define CM_OTPCTL                                                HW_REGISTER_RW( 0x7e101090 ) 
   #define CM_OTPCTL_MASK                                        0x000000b3
   #define CM_OTPCTL_WIDTH                                       8
   #define CM_OTPCTL_RESET                                       0x00000011
      #define CM_OTPCTL_BUSY_BITS                                7:7
      #define CM_OTPCTL_BUSY_SET                                 0x00000080
      #define CM_OTPCTL_BUSY_CLR                                 0xffffff7f
      #define CM_OTPCTL_BUSY_MSB                                 7
      #define CM_OTPCTL_BUSY_LSB                                 7
      #define CM_OTPCTL_KILL_BITS                                5:5
      #define CM_OTPCTL_KILL_SET                                 0x00000020
      #define CM_OTPCTL_KILL_CLR                                 0xffffffdf
      #define CM_OTPCTL_KILL_MSB                                 5
      #define CM_OTPCTL_KILL_LSB                                 5
      #define CM_OTPCTL_ENAB_BITS                                4:4
      #define CM_OTPCTL_ENAB_SET                                 0x00000010
      #define CM_OTPCTL_ENAB_CLR                                 0xffffffef
      #define CM_OTPCTL_ENAB_MSB                                 4
      #define CM_OTPCTL_ENAB_LSB                                 4
      #define CM_OTPCTL_SRC_BITS                                 1:0
      #define CM_OTPCTL_SRC_SET                                  0x00000003
      #define CM_OTPCTL_SRC_CLR                                  0xfffffffc
      #define CM_OTPCTL_SRC_MSB                                  1
      #define CM_OTPCTL_SRC_LSB                                  0
#define CM_OTPDIV                                                HW_REGISTER_RW( 0x7e101094 ) 
   #define CM_OTPDIV_MASK                                        0x0001f000
   #define CM_OTPDIV_WIDTH                                       17
   #define CM_OTPDIV_RESET                                       0x00004000
      #define CM_OTPDIV_DIV_BITS                                 16:12
      #define CM_OTPDIV_DIV_SET                                  0x0001f000
      #define CM_OTPDIV_DIV_CLR                                  0xfffe0fff
      #define CM_OTPDIV_DIV_MSB                                  16
      #define CM_OTPDIV_DIV_LSB                                  12
#define CM_PULSECTL                                              HW_REGISTER_RW( 0x7e101190 ) 
   #define CM_PULSECTL_MASK                                      0x000000b3
   #define CM_PULSECTL_WIDTH                                     8
   #define CM_PULSECTL_RESET                                     0x00000011
      #define CM_PULSECTL_BUSY_BITS                              7:7
      #define CM_PULSECTL_BUSY_SET                               0x00000080
      #define CM_PULSECTL_BUSY_CLR                               0xffffff7f
      #define CM_PULSECTL_BUSY_MSB                               7
      #define CM_PULSECTL_BUSY_LSB                               7
      #define CM_PULSECTL_KILL_BITS                              5:5
      #define CM_PULSECTL_KILL_SET                               0x00000020
      #define CM_PULSECTL_KILL_CLR                               0xffffffdf
      #define CM_PULSECTL_KILL_MSB                               5
      #define CM_PULSECTL_KILL_LSB                               5
      #define CM_PULSECTL_ENAB_BITS                              4:4
      #define CM_PULSECTL_ENAB_SET                               0x00000010
      #define CM_PULSECTL_ENAB_CLR                               0xffffffef
      #define CM_PULSECTL_ENAB_MSB                               4
      #define CM_PULSECTL_ENAB_LSB                               4
      #define CM_PULSECTL_SRC_BITS                               1:0
      #define CM_PULSECTL_SRC_SET                                0x00000003
      #define CM_PULSECTL_SRC_CLR                                0xfffffffc
      #define CM_PULSECTL_SRC_MSB                                1
      #define CM_PULSECTL_SRC_LSB                                0
#define CM_PULSEDIV                                              HW_REGISTER_RW( 0x7e101194 ) 
   #define CM_PULSEDIV_MASK                                      0x00fff000
   #define CM_PULSEDIV_WIDTH                                     24
   #define CM_PULSEDIV_RESET                                     0x00014000
      #define CM_PULSEDIV_DIV_BITS                               23:12
      #define CM_PULSEDIV_DIV_SET                                0x00fff000
      #define CM_PULSEDIV_DIV_CLR                                0xff000fff
      #define CM_PULSEDIV_DIV_MSB                                23
      #define CM_PULSEDIV_DIV_LSB                                12
#define CM_PCMCTL                                                HW_REGISTER_RW( 0x7e101098 ) 
   #define CM_PCMCTL_MASK                                        0x000006bf
   #define CM_PCMCTL_WIDTH                                       11
   #define CM_PCMCTL_RESET                                       0x00000200
      #define CM_PCMCTL_MASH_BITS                                10:9
      #define CM_PCMCTL_MASH_SET                                 0x00000600
      #define CM_PCMCTL_MASH_CLR                                 0xfffff9ff
      #define CM_PCMCTL_MASH_MSB                                 10
      #define CM_PCMCTL_MASH_LSB                                 9
      #define CM_PCMCTL_BUSY_BITS                                7:7
      #define CM_PCMCTL_BUSY_SET                                 0x00000080
      #define CM_PCMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_PCMCTL_BUSY_MSB                                 7
      #define CM_PCMCTL_BUSY_LSB                                 7
      #define CM_PCMCTL_KILL_BITS                                5:5
      #define CM_PCMCTL_KILL_SET                                 0x00000020
      #define CM_PCMCTL_KILL_CLR                                 0xffffffdf
      #define CM_PCMCTL_KILL_MSB                                 5
      #define CM_PCMCTL_KILL_LSB                                 5
      #define CM_PCMCTL_ENAB_BITS                                4:4
      #define CM_PCMCTL_ENAB_SET                                 0x00000010
      #define CM_PCMCTL_ENAB_CLR                                 0xffffffef
      #define CM_PCMCTL_ENAB_MSB                                 4
      #define CM_PCMCTL_ENAB_LSB                                 4
      #define CM_PCMCTL_SRC_BITS                                 3:0
      #define CM_PCMCTL_SRC_SET                                  0x0000000f
      #define CM_PCMCTL_SRC_CLR                                  0xfffffff0
      #define CM_PCMCTL_SRC_MSB                                  3
      #define CM_PCMCTL_SRC_LSB                                  0
#define CM_PCMDIV                                                HW_REGISTER_RW( 0x7e10109c ) 
   #define CM_PCMDIV_MASK                                        0x00ffffff
   #define CM_PCMDIV_WIDTH                                       24
   #define CM_PCMDIV_RESET                                       0000000000
      #define CM_PCMDIV_DIV_BITS                                 23:0
      #define CM_PCMDIV_DIV_SET                                  0x00ffffff
      #define CM_PCMDIV_DIV_CLR                                  0xff000000
      #define CM_PCMDIV_DIV_MSB                                  23
      #define CM_PCMDIV_DIV_LSB                                  0
#define CM_PWMCTL                                                HW_REGISTER_RW( 0x7e1010a0 ) 
   #define CM_PWMCTL_MASK                                        0x000006bf
   #define CM_PWMCTL_WIDTH                                       11
   #define CM_PWMCTL_RESET                                       0x00000200
      #define CM_PWMCTL_MASH_BITS                                10:9
      #define CM_PWMCTL_MASH_SET                                 0x00000600
      #define CM_PWMCTL_MASH_CLR                                 0xfffff9ff
      #define CM_PWMCTL_MASH_MSB                                 10
      #define CM_PWMCTL_MASH_LSB                                 9
      #define CM_PWMCTL_BUSY_BITS                                7:7
      #define CM_PWMCTL_BUSY_SET                                 0x00000080
      #define CM_PWMCTL_BUSY_CLR                                 0xffffff7f
      #define CM_PWMCTL_BUSY_MSB                                 7
      #define CM_PWMCTL_BUSY_LSB                                 7
      #define CM_PWMCTL_KILL_BITS                                5:5
      #define CM_PWMCTL_KILL_SET                                 0x00000020
      #define CM_PWMCTL_KILL_CLR                                 0xffffffdf
      #define CM_PWMCTL_KILL_MSB                                 5
      #define CM_PWMCTL_KILL_LSB                                 5
      #define CM_PWMCTL_ENAB_BITS                                4:4
      #define CM_PWMCTL_ENAB_SET                                 0x00000010
      #define CM_PWMCTL_ENAB_CLR                                 0xffffffef
      #define CM_PWMCTL_ENAB_MSB                                 4
      #define CM_PWMCTL_ENAB_LSB                                 4
      #define CM_PWMCTL_SRC_BITS                                 3:0
      #define CM_PWMCTL_SRC_SET                                  0x0000000f
      #define CM_PWMCTL_SRC_CLR                                  0xfffffff0
      #define CM_PWMCTL_SRC_MSB                                  3
      #define CM_PWMCTL_SRC_LSB                                  0
#define CM_PWMDIV                                                HW_REGISTER_RW( 0x7e1010a4 ) 
   #define CM_PWMDIV_MASK                                        0x00ffffff
   #define CM_PWMDIV_WIDTH                                       24
   #define CM_PWMDIV_RESET                                       0000000000
      #define CM_PWMDIV_DIV_BITS                                 23:0
      #define CM_PWMDIV_DIV_SET                                  0x00ffffff
      #define CM_PWMDIV_DIV_CLR                                  0xff000000
      #define CM_PWMDIV_DIV_MSB                                  23
      #define CM_PWMDIV_DIV_LSB                                  0
#define CM_SLIMCTL                                               HW_REGISTER_RW( 0x7e1010a8 ) 
   #define CM_SLIMCTL_MASK                                       0x000006bf
   #define CM_SLIMCTL_WIDTH                                      11
   #define CM_SLIMCTL_RESET                                      0x00000200
      #define CM_SLIMCTL_MASH_BITS                               10:9
      #define CM_SLIMCTL_MASH_SET                                0x00000600
      #define CM_SLIMCTL_MASH_CLR                                0xfffff9ff
      #define CM_SLIMCTL_MASH_MSB                                10
      #define CM_SLIMCTL_MASH_LSB                                9
      #define CM_SLIMCTL_BUSY_BITS                               7:7
      #define CM_SLIMCTL_BUSY_SET                                0x00000080
      #define CM_SLIMCTL_BUSY_CLR                                0xffffff7f
      #define CM_SLIMCTL_BUSY_MSB                                7
      #define CM_SLIMCTL_BUSY_LSB                                7
      #define CM_SLIMCTL_KILL_BITS                               5:5
      #define CM_SLIMCTL_KILL_SET                                0x00000020
      #define CM_SLIMCTL_KILL_CLR                                0xffffffdf
      #define CM_SLIMCTL_KILL_MSB                                5
      #define CM_SLIMCTL_KILL_LSB                                5
      #define CM_SLIMCTL_ENAB_BITS                               4:4
      #define CM_SLIMCTL_ENAB_SET                                0x00000010
      #define CM_SLIMCTL_ENAB_CLR                                0xffffffef
      #define CM_SLIMCTL_ENAB_MSB                                4
      #define CM_SLIMCTL_ENAB_LSB                                4
      #define CM_SLIMCTL_SRC_BITS                                3:0
      #define CM_SLIMCTL_SRC_SET                                 0x0000000f
      #define CM_SLIMCTL_SRC_CLR                                 0xfffffff0
      #define CM_SLIMCTL_SRC_MSB                                 3
      #define CM_SLIMCTL_SRC_LSB                                 0
#define CM_SLIMDIV                                               HW_REGISTER_RW( 0x7e1010ac ) 
   #define CM_SLIMDIV_MASK                                       0x00ffffff
   #define CM_SLIMDIV_WIDTH                                      24
   #define CM_SLIMDIV_RESET                                      0000000000
      #define CM_SLIMDIV_DIV_BITS                                23:0
      #define CM_SLIMDIV_DIV_SET                                 0x00ffffff
      #define CM_SLIMDIV_DIV_CLR                                 0xff000000
      #define CM_SLIMDIV_DIV_MSB                                 23
      #define CM_SLIMDIV_DIV_LSB                                 0
#define CM_SMICTL                                                HW_REGISTER_RW( 0x7e1010b0 ) 
   #define CM_SMICTL_MASK                                        0x000000bf
   #define CM_SMICTL_WIDTH                                       8
   #define CM_SMICTL_RESET                                       0000000000
      #define CM_SMICTL_BUSY_BITS                                7:7
      #define CM_SMICTL_BUSY_SET                                 0x00000080
      #define CM_SMICTL_BUSY_CLR                                 0xffffff7f
      #define CM_SMICTL_BUSY_MSB                                 7
      #define CM_SMICTL_BUSY_LSB                                 7
      #define CM_SMICTL_KILL_BITS                                5:5
      #define CM_SMICTL_KILL_SET                                 0x00000020
      #define CM_SMICTL_KILL_CLR                                 0xffffffdf
      #define CM_SMICTL_KILL_MSB                                 5
      #define CM_SMICTL_KILL_LSB                                 5
      #define CM_SMICTL_ENAB_BITS                                4:4
      #define CM_SMICTL_ENAB_SET                                 0x00000010
      #define CM_SMICTL_ENAB_CLR                                 0xffffffef
      #define CM_SMICTL_ENAB_MSB                                 4
      #define CM_SMICTL_ENAB_LSB                                 4
      #define CM_SMICTL_SRC_BITS                                 3:0
      #define CM_SMICTL_SRC_SET                                  0x0000000f
      #define CM_SMICTL_SRC_CLR                                  0xfffffff0
      #define CM_SMICTL_SRC_MSB                                  3
      #define CM_SMICTL_SRC_LSB                                  0
#define CM_SMIDIV                                                HW_REGISTER_RW( 0x7e1010b4 ) 
   #define CM_SMIDIV_MASK                                        0x0000fff0
   #define CM_SMIDIV_WIDTH                                       16
   #define CM_SMIDIV_RESET                                       0000000000
      #define CM_SMIDIV_DIV_BITS                                 15:4
      #define CM_SMIDIV_DIV_SET                                  0x0000fff0
      #define CM_SMIDIV_DIV_CLR                                  0xffff000f
      #define CM_SMIDIV_DIV_MSB                                  15
      #define CM_SMIDIV_DIV_LSB                                  4
#define CM_SMPSCTL                                               HW_REGISTER_RW( 0x7e1010b8 ) 
   #define CM_SMPSCTL_MASK                                       0x000000f3
   #define CM_SMPSCTL_WIDTH                                      8
   #define CM_SMPSCTL_RESET                                      0000000000
      #define CM_SMPSCTL_BUSY_BITS                               7:7
      #define CM_SMPSCTL_BUSY_SET                                0x00000080
      #define CM_SMPSCTL_BUSY_CLR                                0xffffff7f
      #define CM_SMPSCTL_BUSY_MSB                                7
      #define CM_SMPSCTL_BUSY_LSB                                7
      #define CM_SMPSCTL_GATE_BITS                               6:6
      #define CM_SMPSCTL_GATE_SET                                0x00000040
      #define CM_SMPSCTL_GATE_CLR                                0xffffffbf
      #define CM_SMPSCTL_GATE_MSB                                6
      #define CM_SMPSCTL_GATE_LSB                                6
      #define CM_SMPSCTL_KILL_BITS                               5:5
      #define CM_SMPSCTL_KILL_SET                                0x00000020
      #define CM_SMPSCTL_KILL_CLR                                0xffffffdf
      #define CM_SMPSCTL_KILL_MSB                                5
      #define CM_SMPSCTL_KILL_LSB                                5
      #define CM_SMPSCTL_ENAB_BITS                               4:4
      #define CM_SMPSCTL_ENAB_SET                                0x00000010
      #define CM_SMPSCTL_ENAB_CLR                                0xffffffef
      #define CM_SMPSCTL_ENAB_MSB                                4
      #define CM_SMPSCTL_ENAB_LSB                                4
      #define CM_SMPSCTL_SRC_BITS                                1:0
      #define CM_SMPSCTL_SRC_SET                                 0x00000003
      #define CM_SMPSCTL_SRC_CLR                                 0xfffffffc
      #define CM_SMPSCTL_SRC_MSB                                 1
      #define CM_SMPSCTL_SRC_LSB                                 0
#define CM_SMPSDIV                                               HW_REGISTER_RW( 0x7e1010bc ) 
   #define CM_SMPSDIV_MASK                                       0x00007000
   #define CM_SMPSDIV_WIDTH                                      15
   #define CM_SMPSDIV_RESET                                      0000000000
      #define CM_SMPSDIV_DIV_BITS                                14:12
      #define CM_SMPSDIV_DIV_SET                                 0x00007000
      #define CM_SMPSDIV_DIV_CLR                                 0xffff8fff
      #define CM_SMPSDIV_DIV_MSB                                 14
      #define CM_SMPSDIV_DIV_LSB                                 12
#define CM_TCNTCTL                                               HW_REGISTER_RW( 0x7e1010c0 ) 
   #define CM_TCNTCTL_MASK                                       0x0000f0ff
   #define CM_TCNTCTL_WIDTH                                      16
   #define CM_TCNTCTL_RESET                                      0000000000
      #define CM_TCNTCTL_SRC1_BITS                               15:12
      #define CM_TCNTCTL_SRC1_SET                                0x0000f000
      #define CM_TCNTCTL_SRC1_CLR                                0xffff0fff
      #define CM_TCNTCTL_SRC1_MSB                                15
      #define CM_TCNTCTL_SRC1_LSB                                12
      #define CM_TCNTCTL_BUSY_BITS                               7:7
      #define CM_TCNTCTL_BUSY_SET                                0x00000080
      #define CM_TCNTCTL_BUSY_CLR                                0xffffff7f
      #define CM_TCNTCTL_BUSY_MSB                                7
      #define CM_TCNTCTL_BUSY_LSB                                7
      #define CM_TCNTCTL_KILL_BITS                               6:6
      #define CM_TCNTCTL_KILL_SET                                0x00000040
      #define CM_TCNTCTL_KILL_CLR                                0xffffffbf
      #define CM_TCNTCTL_KILL_MSB                                6
      #define CM_TCNTCTL_KILL_LSB                                6
      #define CM_TCNTCTL_SRC0_BITS                               5:0
      #define CM_TCNTCTL_SRC0_SET                                0x0000003f
      #define CM_TCNTCTL_SRC0_CLR                                0xffffffc0
      #define CM_TCNTCTL_SRC0_MSB                                5
      #define CM_TCNTCTL_SRC0_LSB                                0
#define CM_TCNTCNT                                               HW_REGISTER_RW( 0x7e1010c4 ) 
   #define CM_TCNTCNT_MASK                                       0x0003ffff
   #define CM_TCNTCNT_WIDTH                                      18
   #define CM_TCNTCNT_RESET                                      0000000000
      #define CM_TCNTCNT_CNT_BITS                                17:0
      #define CM_TCNTCNT_CNT_SET                                 0x0003ffff
      #define CM_TCNTCNT_CNT_CLR                                 0xfffc0000
      #define CM_TCNTCNT_CNT_MSB                                 17
      #define CM_TCNTCNT_CNT_LSB                                 0
#define CM_TECCTL                                                HW_REGISTER_RW( 0x7e1010c8 ) 
   #define CM_TECCTL_MASK                                        0x000000b3
   #define CM_TECCTL_WIDTH                                       8
   #define CM_TECCTL_RESET                                       0000000000
      #define CM_TECCTL_BUSY_BITS                                7:7
      #define CM_TECCTL_BUSY_SET                                 0x00000080
      #define CM_TECCTL_BUSY_CLR                                 0xffffff7f
      #define CM_TECCTL_BUSY_MSB                                 7
      #define CM_TECCTL_BUSY_LSB                                 7
      #define CM_TECCTL_KILL_BITS                                5:5
      #define CM_TECCTL_KILL_SET                                 0x00000020
      #define CM_TECCTL_KILL_CLR                                 0xffffffdf
      #define CM_TECCTL_KILL_MSB                                 5
      #define CM_TECCTL_KILL_LSB                                 5
      #define CM_TECCTL_ENAB_BITS                                4:4
      #define CM_TECCTL_ENAB_SET                                 0x00000010
      #define CM_TECCTL_ENAB_CLR                                 0xffffffef
      #define CM_TECCTL_ENAB_MSB                                 4
      #define CM_TECCTL_ENAB_LSB                                 4
      #define CM_TECCTL_SRC_BITS                                 1:0
      #define CM_TECCTL_SRC_SET                                  0x00000003
      #define CM_TECCTL_SRC_CLR                                  0xfffffffc
      #define CM_TECCTL_SRC_MSB                                  1
      #define CM_TECCTL_SRC_LSB                                  0
#define CM_TECDIV                                                HW_REGISTER_RW( 0x7e1010cc ) 
   #define CM_TECDIV_MASK                                        0x0003f000
   #define CM_TECDIV_WIDTH                                       18
   #define CM_TECDIV_RESET                                       0000000000
      #define CM_TECDIV_DIV_BITS                                 17:12
      #define CM_TECDIV_DIV_SET                                  0x0003f000
      #define CM_TECDIV_DIV_CLR                                  0xfffc0fff
      #define CM_TECDIV_DIV_MSB                                  17
      #define CM_TECDIV_DIV_LSB                                  12
#define CM_TD0CTL                                                HW_REGISTER_RW( 0x7e1010d0 ) 
   #define CM_TD0CTL_MASK                                        0x000011ff
   #define CM_TD0CTL_WIDTH                                       13
   #define CM_TD0CTL_RESET                                       0000000000
      #define CM_TD0CTL_STEP_BITS                                12:12
      #define CM_TD0CTL_STEP_SET                                 0x00001000
      #define CM_TD0CTL_STEP_CLR                                 0xffffefff
      #define CM_TD0CTL_STEP_MSB                                 12
      #define CM_TD0CTL_STEP_LSB                                 12
      #define CM_TD0CTL_FLIP_BITS                                8:8
      #define CM_TD0CTL_FLIP_SET                                 0x00000100
      #define CM_TD0CTL_FLIP_CLR                                 0xfffffeff
      #define CM_TD0CTL_FLIP_MSB                                 8
      #define CM_TD0CTL_FLIP_LSB                                 8
      #define CM_TD0CTL_BUSY_BITS                                7:7
      #define CM_TD0CTL_BUSY_SET                                 0x00000080
      #define CM_TD0CTL_BUSY_CLR                                 0xffffff7f
      #define CM_TD0CTL_BUSY_MSB                                 7
      #define CM_TD0CTL_BUSY_LSB                                 7
      #define CM_TD0CTL_GATE_BITS                                6:6
      #define CM_TD0CTL_GATE_SET                                 0x00000040
      #define CM_TD0CTL_GATE_CLR                                 0xffffffbf
      #define CM_TD0CTL_GATE_MSB                                 6
      #define CM_TD0CTL_GATE_LSB                                 6
      #define CM_TD0CTL_KILL_BITS                                5:5
      #define CM_TD0CTL_KILL_SET                                 0x00000020
      #define CM_TD0CTL_KILL_CLR                                 0xffffffdf
      #define CM_TD0CTL_KILL_MSB                                 5
      #define CM_TD0CTL_KILL_LSB                                 5
      #define CM_TD0CTL_ENAB_BITS                                4:4
      #define CM_TD0CTL_ENAB_SET                                 0x00000010
      #define CM_TD0CTL_ENAB_CLR                                 0xffffffef
      #define CM_TD0CTL_ENAB_MSB                                 4
      #define CM_TD0CTL_ENAB_LSB                                 4
      #define CM_TD0CTL_SRC_BITS                                 3:0
      #define CM_TD0CTL_SRC_SET                                  0x0000000f
      #define CM_TD0CTL_SRC_CLR                                  0xfffffff0
      #define CM_TD0CTL_SRC_MSB                                  3
      #define CM_TD0CTL_SRC_LSB                                  0
#define CM_TD0DIV                                                HW_REGISTER_RW( 0x7e1010d4 ) 
   #define CM_TD0DIV_MASK                                        0x00ffffff
   #define CM_TD0DIV_WIDTH                                       24
   #define CM_TD0DIV_RESET                                       0000000000
      #define CM_TD0DIV_DIV_BITS                                 23:0
      #define CM_TD0DIV_DIV_SET                                  0x00ffffff
      #define CM_TD0DIV_DIV_CLR                                  0xff000000
      #define CM_TD0DIV_DIV_MSB                                  23
      #define CM_TD0DIV_DIV_LSB                                  0
#define CM_TD1CTL                                                HW_REGISTER_RW( 0x7e1010d8 ) 
   #define CM_TD1CTL_MASK                                        0x000011ff
   #define CM_TD1CTL_WIDTH                                       13
   #define CM_TD1CTL_RESET                                       0000000000
      #define CM_TD1CTL_STEP_BITS                                12:12
      #define CM_TD1CTL_STEP_SET                                 0x00001000
      #define CM_TD1CTL_STEP_CLR                                 0xffffefff
      #define CM_TD1CTL_STEP_MSB                                 12
      #define CM_TD1CTL_STEP_LSB                                 12
      #define CM_TD1CTL_FLIP_BITS                                8:8
      #define CM_TD1CTL_FLIP_SET                                 0x00000100
      #define CM_TD1CTL_FLIP_CLR                                 0xfffffeff
      #define CM_TD1CTL_FLIP_MSB                                 8
      #define CM_TD1CTL_FLIP_LSB                                 8
      #define CM_TD1CTL_BUSY_BITS                                7:7
      #define CM_TD1CTL_BUSY_SET                                 0x00000080
      #define CM_TD1CTL_BUSY_CLR                                 0xffffff7f
      #define CM_TD1CTL_BUSY_MSB                                 7
      #define CM_TD1CTL_BUSY_LSB                                 7
      #define CM_TD1CTL_GATE_BITS                                6:6
      #define CM_TD1CTL_GATE_SET                                 0x00000040
      #define CM_TD1CTL_GATE_CLR                                 0xffffffbf
      #define CM_TD1CTL_GATE_MSB                                 6
      #define CM_TD1CTL_GATE_LSB                                 6
      #define CM_TD1CTL_KILL_BITS                                5:5
      #define CM_TD1CTL_KILL_SET                                 0x00000020
      #define CM_TD1CTL_KILL_CLR                                 0xffffffdf
      #define CM_TD1CTL_KILL_MSB                                 5
      #define CM_TD1CTL_KILL_LSB                                 5
      #define CM_TD1CTL_ENAB_BITS                                4:4
      #define CM_TD1CTL_ENAB_SET                                 0x00000010
      #define CM_TD1CTL_ENAB_CLR                                 0xffffffef
      #define CM_TD1CTL_ENAB_MSB                                 4
      #define CM_TD1CTL_ENAB_LSB                                 4
      #define CM_TD1CTL_SRC_BITS                                 3:0
      #define CM_TD1CTL_SRC_SET                                  0x0000000f
      #define CM_TD1CTL_SRC_CLR                                  0xfffffff0
      #define CM_TD1CTL_SRC_MSB                                  3
      #define CM_TD1CTL_SRC_LSB                                  0
#define CM_TD1DIV                                                HW_REGISTER_RW( 0x7e1010dc ) 
   #define CM_TD1DIV_MASK                                        0x00ffffff
   #define CM_TD1DIV_WIDTH                                       24
   #define CM_TD1DIV_RESET                                       0000000000
      #define CM_TD1DIV_DIV_BITS                                 23:0
      #define CM_TD1DIV_DIV_SET                                  0x00ffffff
      #define CM_TD1DIV_DIV_CLR                                  0xff000000
      #define CM_TD1DIV_DIV_MSB                                  23
      #define CM_TD1DIV_DIV_LSB                                  0
#define CM_TSENSCTL                                              HW_REGISTER_RW( 0x7e1010e0 ) 
   #define CM_TSENSCTL_MASK                                      0x000000b3
   #define CM_TSENSCTL_WIDTH                                     8
   #define CM_TSENSCTL_RESET                                     0000000000
      #define CM_TSENSCTL_BUSY_BITS                              7:7
      #define CM_TSENSCTL_BUSY_SET                               0x00000080
      #define CM_TSENSCTL_BUSY_CLR                               0xffffff7f
      #define CM_TSENSCTL_BUSY_MSB                               7
      #define CM_TSENSCTL_BUSY_LSB                               7
      #define CM_TSENSCTL_KILL_BITS                              5:5
      #define CM_TSENSCTL_KILL_SET                               0x00000020
      #define CM_TSENSCTL_KILL_CLR                               0xffffffdf
      #define CM_TSENSCTL_KILL_MSB                               5
      #define CM_TSENSCTL_KILL_LSB                               5
      #define CM_TSENSCTL_ENAB_BITS                              4:4
      #define CM_TSENSCTL_ENAB_SET                               0x00000010
      #define CM_TSENSCTL_ENAB_CLR                               0xffffffef
      #define CM_TSENSCTL_ENAB_MSB                               4
      #define CM_TSENSCTL_ENAB_LSB                               4
      #define CM_TSENSCTL_SRC_BITS                               1:0
      #define CM_TSENSCTL_SRC_SET                                0x00000003
      #define CM_TSENSCTL_SRC_CLR                                0xfffffffc
      #define CM_TSENSCTL_SRC_MSB                                1
      #define CM_TSENSCTL_SRC_LSB                                0
#define CM_TSENSDIV                                              HW_REGISTER_RW( 0x7e1010e4 ) 
   #define CM_TSENSDIV_MASK                                      0x0001f000
   #define CM_TSENSDIV_WIDTH                                     17
   #define CM_TSENSDIV_RESET                                     0000000000
      #define CM_TSENSDIV_DIV_BITS                               16:12
      #define CM_TSENSDIV_DIV_SET                                0x0001f000
      #define CM_TSENSDIV_DIV_CLR                                0xfffe0fff
      #define CM_TSENSDIV_DIV_MSB                                16
      #define CM_TSENSDIV_DIV_LSB                                12
#define CM_TIMERCTL                                              HW_REGISTER_RW( 0x7e1010e8 ) 
   #define CM_TIMERCTL_MASK                                      0x000000b3
   #define CM_TIMERCTL_WIDTH                                     8
   #define CM_TIMERCTL_RESET                                     0000000000
      #define CM_TIMERCTL_BUSY_BITS                              7:7
      #define CM_TIMERCTL_BUSY_SET                               0x00000080
      #define CM_TIMERCTL_BUSY_CLR                               0xffffff7f
      #define CM_TIMERCTL_BUSY_MSB                               7
      #define CM_TIMERCTL_BUSY_LSB                               7
      #define CM_TIMERCTL_KILL_BITS                              5:5
      #define CM_TIMERCTL_KILL_SET                               0x00000020
      #define CM_TIMERCTL_KILL_CLR                               0xffffffdf
      #define CM_TIMERCTL_KILL_MSB                               5
      #define CM_TIMERCTL_KILL_LSB                               5
      #define CM_TIMERCTL_ENAB_BITS                              4:4
      #define CM_TIMERCTL_ENAB_SET                               0x00000010
      #define CM_TIMERCTL_ENAB_CLR                               0xffffffef
      #define CM_TIMERCTL_ENAB_MSB                               4
      #define CM_TIMERCTL_ENAB_LSB                               4
      #define CM_TIMERCTL_SRC_BITS                               1:0
      #define CM_TIMERCTL_SRC_SET                                0x00000003
      #define CM_TIMERCTL_SRC_CLR                                0xfffffffc
      #define CM_TIMERCTL_SRC_MSB                                1
      #define CM_TIMERCTL_SRC_LSB                                0
#define CM_TIMERDIV                                              HW_REGISTER_RW( 0x7e1010ec ) 
   #define CM_TIMERDIV_MASK                                      0x0003ffff
   #define CM_TIMERDIV_WIDTH                                     18
   #define CM_TIMERDIV_RESET                                     0000000000
      #define CM_TIMERDIV_DIV_BITS                               17:0
      #define CM_TIMERDIV_DIV_SET                                0x0003ffff
      #define CM_TIMERDIV_DIV_CLR                                0xfffc0000
      #define CM_TIMERDIV_DIV_MSB                                17
      #define CM_TIMERDIV_DIV_LSB                                0
#define CM_UARTCTL                                               HW_REGISTER_RW( 0x7e1010f0 ) 
   #define CM_UARTCTL_MASK                                       0x000000bf
   #define CM_UARTCTL_WIDTH                                      8
   #define CM_UARTCTL_RESET                                      0000000000
      #define CM_UARTCTL_BUSY_BITS                               7:7
      #define CM_UARTCTL_BUSY_SET                                0x00000080
      #define CM_UARTCTL_BUSY_CLR                                0xffffff7f
      #define CM_UARTCTL_BUSY_MSB                                7
      #define CM_UARTCTL_BUSY_LSB                                7
      #define CM_UARTCTL_KILL_BITS                               5:5
      #define CM_UARTCTL_KILL_SET                                0x00000020
      #define CM_UARTCTL_KILL_CLR                                0xffffffdf
      #define CM_UARTCTL_KILL_MSB                                5
      #define CM_UARTCTL_KILL_LSB                                5
      #define CM_UARTCTL_ENAB_BITS                               4:4
      #define CM_UARTCTL_ENAB_SET                                0x00000010
      #define CM_UARTCTL_ENAB_CLR                                0xffffffef
      #define CM_UARTCTL_ENAB_MSB                                4
      #define CM_UARTCTL_ENAB_LSB                                4
      #define CM_UARTCTL_SRC_BITS                                3:0
      #define CM_UARTCTL_SRC_SET                                 0x0000000f
      #define CM_UARTCTL_SRC_CLR                                 0xfffffff0
      #define CM_UARTCTL_SRC_MSB                                 3
      #define CM_UARTCTL_SRC_LSB                                 0
#define CM_UARTDIV                                               HW_REGISTER_RW( 0x7e1010f4 ) 
   #define CM_UARTDIV_MASK                                       0x003fffff
   #define CM_UARTDIV_WIDTH                                      22
   #define CM_UARTDIV_RESET                                      0000000000
      #define CM_UARTDIV_DIV_BITS                                21:0
      #define CM_UARTDIV_DIV_SET                                 0x003fffff
      #define CM_UARTDIV_DIV_CLR                                 0xffc00000
      #define CM_UARTDIV_DIV_MSB                                 21
      #define CM_UARTDIV_DIV_LSB                                 0
#define CM_VECCTL                                                HW_REGISTER_RW( 0x7e1010f8 ) 
   #define CM_VECCTL_MASK                                        0x000000bf
   #define CM_VECCTL_WIDTH                                       8
   #define CM_VECCTL_RESET                                       0000000000
      #define CM_VECCTL_BUSY_BITS                                7:7
      #define CM_VECCTL_BUSY_SET                                 0x00000080
      #define CM_VECCTL_BUSY_CLR                                 0xffffff7f
      #define CM_VECCTL_BUSY_MSB                                 7
      #define CM_VECCTL_BUSY_LSB                                 7
      #define CM_VECCTL_KILL_BITS                                5:5
      #define CM_VECCTL_KILL_SET                                 0x00000020
      #define CM_VECCTL_KILL_CLR                                 0xffffffdf
      #define CM_VECCTL_KILL_MSB                                 5
      #define CM_VECCTL_KILL_LSB                                 5
      #define CM_VECCTL_ENAB_BITS                                4:4
      #define CM_VECCTL_ENAB_SET                                 0x00000010
      #define CM_VECCTL_ENAB_CLR                                 0xffffffef
      #define CM_VECCTL_ENAB_MSB                                 4
      #define CM_VECCTL_ENAB_LSB                                 4
      #define CM_VECCTL_SRC_BITS                                 3:0
      #define CM_VECCTL_SRC_SET                                  0x0000000f
      #define CM_VECCTL_SRC_CLR                                  0xfffffff0
      #define CM_VECCTL_SRC_MSB                                  3
      #define CM_VECCTL_SRC_LSB                                  0
#define CM_VECDIV                                                HW_REGISTER_RW( 0x7e1010fc ) 
   #define CM_VECDIV_MASK                                        0x0000f000
   #define CM_VECDIV_WIDTH                                       16
   #define CM_VECDIV_RESET                                       0000000000
      #define CM_VECDIV_DIV_BITS                                 15:12
      #define CM_VECDIV_DIV_SET                                  0x0000f000
      #define CM_VECDIV_DIV_CLR                                  0xffff0fff
      #define CM_VECDIV_DIV_MSB                                  15
      #define CM_VECDIV_DIV_LSB                                  12
#define CM_AVEOCTL                                               HW_REGISTER_RW( 0x7e1011b8 ) 
   #define CM_AVEOCTL_MASK                                       0x000000bf
   #define CM_AVEOCTL_WIDTH                                      8
   #define CM_AVEOCTL_RESET                                      0000000000
      #define CM_AVEOCTL_BUSY_BITS                               7:7
      #define CM_AVEOCTL_BUSY_SET                                0x00000080
      #define CM_AVEOCTL_BUSY_CLR                                0xffffff7f
      #define CM_AVEOCTL_BUSY_MSB                                7
      #define CM_AVEOCTL_BUSY_LSB                                7
      #define CM_AVEOCTL_KILL_BITS                               5:5
      #define CM_AVEOCTL_KILL_SET                                0x00000020
      #define CM_AVEOCTL_KILL_CLR                                0xffffffdf
      #define CM_AVEOCTL_KILL_MSB                                5
      #define CM_AVEOCTL_KILL_LSB                                5
      #define CM_AVEOCTL_ENAB_BITS                               4:4
      #define CM_AVEOCTL_ENAB_SET                                0x00000010
      #define CM_AVEOCTL_ENAB_CLR                                0xffffffef
      #define CM_AVEOCTL_ENAB_MSB                                4
      #define CM_AVEOCTL_ENAB_LSB                                4
      #define CM_AVEOCTL_SRC_BITS                                3:0
      #define CM_AVEOCTL_SRC_SET                                 0x0000000f
      #define CM_AVEOCTL_SRC_CLR                                 0xfffffff0
      #define CM_AVEOCTL_SRC_MSB                                 3
      #define CM_AVEOCTL_SRC_LSB                                 0
#define CM_AVEODIV                                               HW_REGISTER_RW( 0x7e1011bc ) 
   #define CM_AVEODIV_MASK                                       0x0000f000
   #define CM_AVEODIV_WIDTH                                      16
   #define CM_AVEODIV_RESET                                      0000000000
      #define CM_AVEODIV_DIV_BITS                                15:12
      #define CM_AVEODIV_DIV_SET                                 0x0000f000
      #define CM_AVEODIV_DIV_CLR                                 0xffff0fff
      #define CM_AVEODIV_DIV_MSB                                 15
      #define CM_AVEODIV_DIV_LSB                                 12
#define CM_EMMCCTL                                               HW_REGISTER_RW( 0x7e1011c0 ) 
   #define CM_EMMCCTL_MASK                                       0x000000bf
   #define CM_EMMCCTL_WIDTH                                      8
   #define CM_EMMCCTL_RESET                                      0000000000
      #define CM_EMMCCTL_BUSY_BITS                               7:7
      #define CM_EMMCCTL_BUSY_SET                                0x00000080
      #define CM_EMMCCTL_BUSY_CLR                                0xffffff7f
      #define CM_EMMCCTL_BUSY_MSB                                7
      #define CM_EMMCCTL_BUSY_LSB                                7
      #define CM_EMMCCTL_KILL_BITS                               5:5
      #define CM_EMMCCTL_KILL_SET                                0x00000020
      #define CM_EMMCCTL_KILL_CLR                                0xffffffdf
      #define CM_EMMCCTL_KILL_MSB                                5
      #define CM_EMMCCTL_KILL_LSB                                5
      #define CM_EMMCCTL_ENAB_BITS                               4:4
      #define CM_EMMCCTL_ENAB_SET                                0x00000010
      #define CM_EMMCCTL_ENAB_CLR                                0xffffffef
      #define CM_EMMCCTL_ENAB_MSB                                4
      #define CM_EMMCCTL_ENAB_LSB                                4
      #define CM_EMMCCTL_SRC_BITS                                3:0
      #define CM_EMMCCTL_SRC_SET                                 0x0000000f
      #define CM_EMMCCTL_SRC_CLR                                 0xfffffff0
      #define CM_EMMCCTL_SRC_MSB                                 3
      #define CM_EMMCCTL_SRC_LSB                                 0
#define CM_EMMCDIV                                               HW_REGISTER_RW( 0x7e1011c4 ) 
   #define CM_EMMCDIV_MASK                                       0x0000fff0
   #define CM_EMMCDIV_WIDTH                                      16
   #define CM_EMMCDIV_RESET                                      0000000000
      #define CM_EMMCDIV_DIV_BITS                                15:4
      #define CM_EMMCDIV_DIV_SET                                 0x0000fff0
      #define CM_EMMCDIV_DIV_CLR                                 0xffff000f
      #define CM_EMMCDIV_DIV_MSB                                 15
      #define CM_EMMCDIV_DIV_LSB                                 4
#define CM_OSCCOUNT                                              HW_REGISTER_RW( 0x7e101100 ) 
   #define CM_OSCCOUNT_MASK                                      0x0000ffff
   #define CM_OSCCOUNT_WIDTH                                     16
   #define CM_OSCCOUNT_RESET                                     0000000000
      #define CM_OSCCOUNT_NUM_BITS                               15:0
      #define CM_OSCCOUNT_NUM_SET                                0x0000ffff
      #define CM_OSCCOUNT_NUM_CLR                                0xffff0000
      #define CM_OSCCOUNT_NUM_MSB                                15
      #define CM_OSCCOUNT_NUM_LSB                                0
#define CM_PLLA                                                  HW_REGISTER_RW( 0x7e101104 ) 
   #define CM_PLLA_MASK                                          0x000003ff
   #define CM_PLLA_WIDTH                                         10
   #define CM_PLLA_RESET                                         0x00000300
      #define CM_PLLA_DIGRST_BITS                                9:9
      #define CM_PLLA_DIGRST_SET                                 0x00000200
      #define CM_PLLA_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLA_DIGRST_MSB                                 9
      #define CM_PLLA_DIGRST_LSB                                 9
      #define CM_PLLA_ANARST_BITS                                8:8
      #define CM_PLLA_ANARST_SET                                 0x00000100
      #define CM_PLLA_ANARST_CLR                                 0xfffffeff
      #define CM_PLLA_ANARST_MSB                                 8
      #define CM_PLLA_ANARST_LSB                                 8
      #define CM_PLLA_HOLDPER_BITS                               7:7
      #define CM_PLLA_HOLDPER_SET                                0x00000080
      #define CM_PLLA_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLA_HOLDPER_MSB                                7
      #define CM_PLLA_HOLDPER_LSB                                7
      #define CM_PLLA_LOADPER_BITS                               6:6
      #define CM_PLLA_LOADPER_SET                                0x00000040
      #define CM_PLLA_LOADPER_CLR                                0xffffffbf
      #define CM_PLLA_LOADPER_MSB                                6
      #define CM_PLLA_LOADPER_LSB                                6
      #define CM_PLLA_HOLDCORE_BITS                              5:5
      #define CM_PLLA_HOLDCORE_SET                               0x00000020
      #define CM_PLLA_HOLDCORE_CLR                               0xffffffdf
      #define CM_PLLA_HOLDCORE_MSB                               5
      #define CM_PLLA_HOLDCORE_LSB                               5
      #define CM_PLLA_LOADCORE_BITS                              4:4
      #define CM_PLLA_LOADCORE_SET                               0x00000010
      #define CM_PLLA_LOADCORE_CLR                               0xffffffef
      #define CM_PLLA_LOADCORE_MSB                               4
      #define CM_PLLA_LOADCORE_LSB                               4
      #define CM_PLLA_HOLDCCP2_BITS                              3:3
      #define CM_PLLA_HOLDCCP2_SET                               0x00000008
      #define CM_PLLA_HOLDCCP2_CLR                               0xfffffff7
      #define CM_PLLA_HOLDCCP2_MSB                               3
      #define CM_PLLA_HOLDCCP2_LSB                               3
      #define CM_PLLA_LOADCCP2_BITS                              2:2
      #define CM_PLLA_LOADCCP2_SET                               0x00000004
      #define CM_PLLA_LOADCCP2_CLR                               0xfffffffb
      #define CM_PLLA_LOADCCP2_MSB                               2
      #define CM_PLLA_LOADCCP2_LSB                               2
      #define CM_PLLA_HOLDDSI0_BITS                              1:1
      #define CM_PLLA_HOLDDSI0_SET                               0x00000002
      #define CM_PLLA_HOLDDSI0_CLR                               0xfffffffd
      #define CM_PLLA_HOLDDSI0_MSB                               1
      #define CM_PLLA_HOLDDSI0_LSB                               1
      #define CM_PLLA_LOADDSI0_BITS                              0:0
      #define CM_PLLA_LOADDSI0_SET                               0x00000001
      #define CM_PLLA_LOADDSI0_CLR                               0xfffffffe
      #define CM_PLLA_LOADDSI0_MSB                               0
      #define CM_PLLA_LOADDSI0_LSB                               0
#define CM_PLLC                                                  HW_REGISTER_RW( 0x7e101108 ) 
   #define CM_PLLC_MASK                                          0x000003ff
   #define CM_PLLC_WIDTH                                         10
   #define CM_PLLC_RESET                                         0x00000300
      #define CM_PLLC_DIGRST_BITS                                9:9
      #define CM_PLLC_DIGRST_SET                                 0x00000200
      #define CM_PLLC_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLC_DIGRST_MSB                                 9
      #define CM_PLLC_DIGRST_LSB                                 9
      #define CM_PLLC_ANARST_BITS                                8:8
      #define CM_PLLC_ANARST_SET                                 0x00000100
      #define CM_PLLC_ANARST_CLR                                 0xfffffeff
      #define CM_PLLC_ANARST_MSB                                 8
      #define CM_PLLC_ANARST_LSB                                 8
      #define CM_PLLC_HOLDPER_BITS                               7:7
      #define CM_PLLC_HOLDPER_SET                                0x00000080
      #define CM_PLLC_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLC_HOLDPER_MSB                                7
      #define CM_PLLC_HOLDPER_LSB                                7
      #define CM_PLLC_LOADPER_BITS                               6:6
      #define CM_PLLC_LOADPER_SET                                0x00000040
      #define CM_PLLC_LOADPER_CLR                                0xffffffbf
      #define CM_PLLC_LOADPER_MSB                                6
      #define CM_PLLC_LOADPER_LSB                                6
      #define CM_PLLC_HOLDCORE2_BITS                             5:5
      #define CM_PLLC_HOLDCORE2_SET                              0x00000020
      #define CM_PLLC_HOLDCORE2_CLR                              0xffffffdf
      #define CM_PLLC_HOLDCORE2_MSB                              5
      #define CM_PLLC_HOLDCORE2_LSB                              5
      #define CM_PLLC_LOADCORE2_BITS                             4:4
      #define CM_PLLC_LOADCORE2_SET                              0x00000010
      #define CM_PLLC_LOADCORE2_CLR                              0xffffffef
      #define CM_PLLC_LOADCORE2_MSB                              4
      #define CM_PLLC_LOADCORE2_LSB                              4
      #define CM_PLLC_HOLDCORE1_BITS                             3:3
      #define CM_PLLC_HOLDCORE1_SET                              0x00000008
      #define CM_PLLC_HOLDCORE1_CLR                              0xfffffff7
      #define CM_PLLC_HOLDCORE1_MSB                              3
      #define CM_PLLC_HOLDCORE1_LSB                              3
      #define CM_PLLC_LOADCORE1_BITS                             2:2
      #define CM_PLLC_LOADCORE1_SET                              0x00000004
      #define CM_PLLC_LOADCORE1_CLR                              0xfffffffb
      #define CM_PLLC_LOADCORE1_MSB                              2
      #define CM_PLLC_LOADCORE1_LSB                              2
      #define CM_PLLC_HOLDCORE0_BITS                             1:1
      #define CM_PLLC_HOLDCORE0_SET                              0x00000002
      #define CM_PLLC_HOLDCORE0_CLR                              0xfffffffd
      #define CM_PLLC_HOLDCORE0_MSB                              1
      #define CM_PLLC_HOLDCORE0_LSB                              1
      #define CM_PLLC_LOADCORE0_BITS                             0:0
      #define CM_PLLC_LOADCORE0_SET                              0x00000001
      #define CM_PLLC_LOADCORE0_CLR                              0xfffffffe
      #define CM_PLLC_LOADCORE0_MSB                              0
      #define CM_PLLC_LOADCORE0_LSB                              0
#define CM_PLLD                                                  HW_REGISTER_RW( 0x7e10110c ) 
   #define CM_PLLD_MASK                                          0x000003ff
   #define CM_PLLD_WIDTH                                         10
   #define CM_PLLD_RESET                                         0x00000300
      #define CM_PLLD_DIGRST_BITS                                9:9
      #define CM_PLLD_DIGRST_SET                                 0x00000200
      #define CM_PLLD_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLD_DIGRST_MSB                                 9
      #define CM_PLLD_DIGRST_LSB                                 9
      #define CM_PLLD_ANARST_BITS                                8:8
      #define CM_PLLD_ANARST_SET                                 0x00000100
      #define CM_PLLD_ANARST_CLR                                 0xfffffeff
      #define CM_PLLD_ANARST_MSB                                 8
      #define CM_PLLD_ANARST_LSB                                 8
      #define CM_PLLD_HOLDPER_BITS                               7:7
      #define CM_PLLD_HOLDPER_SET                                0x00000080
      #define CM_PLLD_HOLDPER_CLR                                0xffffff7f
      #define CM_PLLD_HOLDPER_MSB                                7
      #define CM_PLLD_HOLDPER_LSB                                7
      #define CM_PLLD_LOADPER_BITS                               6:6
      #define CM_PLLD_LOADPER_SET                                0x00000040
      #define CM_PLLD_LOADPER_CLR                                0xffffffbf
      #define CM_PLLD_LOADPER_MSB                                6
      #define CM_PLLD_LOADPER_LSB                                6
      #define CM_PLLD_HOLDCORE_BITS                              5:5
      #define CM_PLLD_HOLDCORE_SET                               0x00000020
      #define CM_PLLD_HOLDCORE_CLR                               0xffffffdf
      #define CM_PLLD_HOLDCORE_MSB                               5
      #define CM_PLLD_HOLDCORE_LSB                               5
      #define CM_PLLD_LOADCORE_BITS                              4:4
      #define CM_PLLD_LOADCORE_SET                               0x00000010
      #define CM_PLLD_LOADCORE_CLR                               0xffffffef
      #define CM_PLLD_LOADCORE_MSB                               4
      #define CM_PLLD_LOADCORE_LSB                               4
      #define CM_PLLD_HOLDDSI1_BITS                              3:3
      #define CM_PLLD_HOLDDSI1_SET                               0x00000008
      #define CM_PLLD_HOLDDSI1_CLR                               0xfffffff7
      #define CM_PLLD_HOLDDSI1_MSB                               3
      #define CM_PLLD_HOLDDSI1_LSB                               3
      #define CM_PLLD_LOADDSI1_BITS                              2:2
      #define CM_PLLD_LOADDSI1_SET                               0x00000004
      #define CM_PLLD_LOADDSI1_CLR                               0xfffffffb
      #define CM_PLLD_LOADDSI1_MSB                               2
      #define CM_PLLD_LOADDSI1_LSB                               2
      #define CM_PLLD_HOLDDSI0_BITS                              1:1
      #define CM_PLLD_HOLDDSI0_SET                               0x00000002
      #define CM_PLLD_HOLDDSI0_CLR                               0xfffffffd
      #define CM_PLLD_HOLDDSI0_MSB                               1
      #define CM_PLLD_HOLDDSI0_LSB                               1
      #define CM_PLLD_LOADDSI0_BITS                              0:0
      #define CM_PLLD_LOADDSI0_SET                               0x00000001
      #define CM_PLLD_LOADDSI0_CLR                               0xfffffffe
      #define CM_PLLD_LOADDSI0_MSB                               0
      #define CM_PLLD_LOADDSI0_LSB                               0
#define CM_PLLH                                                  HW_REGISTER_RW( 0x7e101110 ) 
   #define CM_PLLH_MASK                                          0x00000307
   #define CM_PLLH_WIDTH                                         10
   #define CM_PLLH_RESET                                         0x00000300
      #define CM_PLLH_DIGRST_BITS                                9:9
      #define CM_PLLH_DIGRST_SET                                 0x00000200
      #define CM_PLLH_DIGRST_CLR                                 0xfffffdff
      #define CM_PLLH_DIGRST_MSB                                 9
      #define CM_PLLH_DIGRST_LSB                                 9
      #define CM_PLLH_ANARST_BITS                                8:8
      #define CM_PLLH_ANARST_SET                                 0x00000100
      #define CM_PLLH_ANARST_CLR                                 0xfffffeff
      #define CM_PLLH_ANARST_MSB                                 8
      #define CM_PLLH_ANARST_LSB                                 8
      #define CM_PLLH_LOADRCAL_BITS                              2:2
      #define CM_PLLH_LOADRCAL_SET                               0x00000004
      #define CM_PLLH_LOADRCAL_CLR                               0xfffffffb
      #define CM_PLLH_LOADRCAL_MSB                               2
      #define CM_PLLH_LOADRCAL_LSB                               2
      #define CM_PLLH_LOADAUX_BITS                               1:1
      #define CM_PLLH_LOADAUX_SET                                0x00000002
      #define CM_PLLH_LOADAUX_CLR                                0xfffffffd
      #define CM_PLLH_LOADAUX_MSB                                1
      #define CM_PLLH_LOADAUX_LSB                                1
      #define CM_PLLH_LOADPIX_BITS                               0:0
      #define CM_PLLH_LOADPIX_SET                                0x00000001
      #define CM_PLLH_LOADPIX_CLR                                0xfffffffe
      #define CM_PLLH_LOADPIX_MSB                                0
      #define CM_PLLH_LOADPIX_LSB                                0
#define CM_LOCK                                                  HW_REGISTER_RW( 0x7e101114 ) 
   #define CM_LOCK_MASK                                          0x000000ff
   #define CM_LOCK_WIDTH                                         8
   #define CM_LOCK_RESET                                         0000000000
      #define CM_LOCK_FLOCKH_BITS                                7:7
      #define CM_LOCK_FLOCKH_SET                                 0x00000080
      #define CM_LOCK_FLOCKH_CLR                                 0xffffff7f
      #define CM_LOCK_FLOCKH_MSB                                 7
      #define CM_LOCK_FLOCKH_LSB                                 7
      #define CM_LOCK_FLOCKD_BITS                                6:6
      #define CM_LOCK_FLOCKD_SET                                 0x00000040
      #define CM_LOCK_FLOCKD_CLR                                 0xffffffbf
      #define CM_LOCK_FLOCKD_MSB                                 6
      #define CM_LOCK_FLOCKD_LSB                                 6
      #define CM_LOCK_FLOCKA_BITS                                5:5
      #define CM_LOCK_FLOCKA_SET                                 0x00000020
      #define CM_LOCK_FLOCKA_CLR                                 0xffffffdf
      #define CM_LOCK_FLOCKA_MSB                                 5
      #define CM_LOCK_FLOCKA_LSB                                 5
      #define CM_LOCK_FLOCKC_BITS                                4:4
      #define CM_LOCK_FLOCKC_SET                                 0x00000010
      #define CM_LOCK_FLOCKC_CLR                                 0xffffffef
      #define CM_LOCK_FLOCKC_MSB                                 4
      #define CM_LOCK_FLOCKC_LSB                                 4
      #define CM_LOCK_LOCKH_BITS                                 3:3
      #define CM_LOCK_LOCKH_SET                                  0x00000008
      #define CM_LOCK_LOCKH_CLR                                  0xfffffff7
      #define CM_LOCK_LOCKH_MSB                                  3
      #define CM_LOCK_LOCKH_LSB                                  3
      #define CM_LOCK_LOCKD_BITS                                 2:2
      #define CM_LOCK_LOCKD_SET                                  0x00000004
      #define CM_LOCK_LOCKD_CLR                                  0xfffffffb
      #define CM_LOCK_LOCKD_MSB                                  2
      #define CM_LOCK_LOCKD_LSB                                  2
      #define CM_LOCK_LOCKA_BITS                                 1:1
      #define CM_LOCK_LOCKA_SET                                  0x00000002
      #define CM_LOCK_LOCKA_CLR                                  0xfffffffd
      #define CM_LOCK_LOCKA_MSB                                  1
      #define CM_LOCK_LOCKA_LSB                                  1
      #define CM_LOCK_LOCKC_BITS                                 0:0
      #define CM_LOCK_LOCKC_SET                                  0x00000001
      #define CM_LOCK_LOCKC_CLR                                  0xfffffffe
      #define CM_LOCK_LOCKC_MSB                                  0
      #define CM_LOCK_LOCKC_LSB                                  0
#define CM_EVENT                                                 HW_REGISTER_RW( 0x7e101118 ) 
   #define CM_EVENT_MASK                                         0x001fffff
   #define CM_EVENT_WIDTH                                        21
   #define CM_EVENT_RESET                                        0000000000
      #define CM_EVENT_RESUS_BITS                                20:20
      #define CM_EVENT_RESUS_SET                                 0x00100000
      #define CM_EVENT_RESUS_CLR                                 0xffefffff
      #define CM_EVENT_RESUS_MSB                                 20
      #define CM_EVENT_RESUS_LSB                                 20
      #define CM_EVENT_OCDONE_BITS                               19:19
      #define CM_EVENT_OCDONE_SET                                0x00080000
      #define CM_EVENT_OCDONE_CLR                                0xfff7ffff
      #define CM_EVENT_OCDONE_MSB                                19
      #define CM_EVENT_OCDONE_LSB                                19
      #define CM_EVENT_A2WDONE_BITS                              18:18
      #define CM_EVENT_A2WDONE_SET                               0x00040000
      #define CM_EVENT_A2WDONE_CLR                               0xfffbffff
      #define CM_EVENT_A2WDONE_MSB                               18
      #define CM_EVENT_A2WDONE_LSB                               18
      #define CM_EVENT_WRFAIL_BITS                               17:17
      #define CM_EVENT_WRFAIL_SET                                0x00020000
      #define CM_EVENT_WRFAIL_CLR                                0xfffdffff
      #define CM_EVENT_WRFAIL_MSB                                17
      #define CM_EVENT_WRFAIL_LSB                                17
      #define CM_EVENT_BADPASS_BITS                              16:16
      #define CM_EVENT_BADPASS_SET                               0x00010000
      #define CM_EVENT_BADPASS_CLR                               0xfffeffff
      #define CM_EVENT_BADPASS_MSB                               16
      #define CM_EVENT_BADPASS_LSB                               16
      #define CM_EVENT_FLOSSH_BITS                               15:15
      #define CM_EVENT_FLOSSH_SET                                0x00008000
      #define CM_EVENT_FLOSSH_CLR                                0xffff7fff
      #define CM_EVENT_FLOSSH_MSB                                15
      #define CM_EVENT_FLOSSH_LSB                                15
      #define CM_EVENT_FLOSSD_BITS                               14:14
      #define CM_EVENT_FLOSSD_SET                                0x00004000
      #define CM_EVENT_FLOSSD_CLR                                0xffffbfff
      #define CM_EVENT_FLOSSD_MSB                                14
      #define CM_EVENT_FLOSSD_LSB                                14
      #define CM_EVENT_FLOSSA_BITS                               13:13
      #define CM_EVENT_FLOSSA_SET                                0x00002000
      #define CM_EVENT_FLOSSA_CLR                                0xffffdfff
      #define CM_EVENT_FLOSSA_MSB                                13
      #define CM_EVENT_FLOSSA_LSB                                13
      #define CM_EVENT_FLOSSC_BITS                               12:12
      #define CM_EVENT_FLOSSC_SET                                0x00001000
      #define CM_EVENT_FLOSSC_CLR                                0xffffefff
      #define CM_EVENT_FLOSSC_MSB                                12
      #define CM_EVENT_FLOSSC_LSB                                12
      #define CM_EVENT_FGAINH_BITS                               11:11
      #define CM_EVENT_FGAINH_SET                                0x00000800
      #define CM_EVENT_FGAINH_CLR                                0xfffff7ff
      #define CM_EVENT_FGAINH_MSB                                11
      #define CM_EVENT_FGAINH_LSB                                11
      #define CM_EVENT_FGAIND_BITS                               10:10
      #define CM_EVENT_FGAIND_SET                                0x00000400
      #define CM_EVENT_FGAIND_CLR                                0xfffffbff
      #define CM_EVENT_FGAIND_MSB                                10
      #define CM_EVENT_FGAIND_LSB                                10
      #define CM_EVENT_FGAINA_BITS                               9:9
      #define CM_EVENT_FGAINA_SET                                0x00000200
      #define CM_EVENT_FGAINA_CLR                                0xfffffdff
      #define CM_EVENT_FGAINA_MSB                                9
      #define CM_EVENT_FGAINA_LSB                                9
      #define CM_EVENT_FGAINC_BITS                               8:8
      #define CM_EVENT_FGAINC_SET                                0x00000100
      #define CM_EVENT_FGAINC_CLR                                0xfffffeff
      #define CM_EVENT_FGAINC_MSB                                8
      #define CM_EVENT_FGAINC_LSB                                8
      #define CM_EVENT_LOSSH_BITS                                7:7
      #define CM_EVENT_LOSSH_SET                                 0x00000080
      #define CM_EVENT_LOSSH_CLR                                 0xffffff7f
      #define CM_EVENT_LOSSH_MSB                                 7
      #define CM_EVENT_LOSSH_LSB                                 7
      #define CM_EVENT_LOSSD_BITS                                6:6
      #define CM_EVENT_LOSSD_SET                                 0x00000040
      #define CM_EVENT_LOSSD_CLR                                 0xffffffbf
      #define CM_EVENT_LOSSD_MSB                                 6
      #define CM_EVENT_LOSSD_LSB                                 6
      #define CM_EVENT_LOSSA_BITS                                5:5
      #define CM_EVENT_LOSSA_SET                                 0x00000020
      #define CM_EVENT_LOSSA_CLR                                 0xffffffdf
      #define CM_EVENT_LOSSA_MSB                                 5
      #define CM_EVENT_LOSSA_LSB                                 5
      #define CM_EVENT_LOSSC_BITS                                4:4
      #define CM_EVENT_LOSSC_SET                                 0x00000010
      #define CM_EVENT_LOSSC_CLR                                 0xffffffef
      #define CM_EVENT_LOSSC_MSB                                 4
      #define CM_EVENT_LOSSC_LSB                                 4
      #define CM_EVENT_GAINH_BITS                                3:3
      #define CM_EVENT_GAINH_SET                                 0x00000008
      #define CM_EVENT_GAINH_CLR                                 0xfffffff7
      #define CM_EVENT_GAINH_MSB                                 3
      #define CM_EVENT_GAINH_LSB                                 3
      #define CM_EVENT_GAIND_BITS                                2:2
      #define CM_EVENT_GAIND_SET                                 0x00000004
      #define CM_EVENT_GAIND_CLR                                 0xfffffffb
      #define CM_EVENT_GAIND_MSB                                 2
      #define CM_EVENT_GAIND_LSB                                 2
      #define CM_EVENT_GAINA_BITS                                1:1
      #define CM_EVENT_GAINA_SET                                 0x00000002
      #define CM_EVENT_GAINA_CLR                                 0xfffffffd
      #define CM_EVENT_GAINA_MSB                                 1
      #define CM_EVENT_GAINA_LSB                                 1
      #define CM_EVENT_GAINC_BITS                                0:0
      #define CM_EVENT_GAINC_SET                                 0x00000001
      #define CM_EVENT_GAINC_CLR                                 0xfffffffe
      #define CM_EVENT_GAINC_MSB                                 0
      #define CM_EVENT_GAINC_LSB                                 0
#define CM_INTEN                                                 HW_REGISTER_RW( 0x7e10111c ) 
   #define CM_INTEN_MASK                                         0x001fffff
   #define CM_INTEN_WIDTH                                        21
   #define CM_INTEN_RESET                                        0000000000
      #define CM_INTEN_RESUS_BITS                                20:20
      #define CM_INTEN_RESUS_SET                                 0x00100000
      #define CM_INTEN_RESUS_CLR                                 0xffefffff
      #define CM_INTEN_RESUS_MSB                                 20
      #define CM_INTEN_RESUS_LSB                                 20
      #define CM_INTEN_OCDONE_BITS                               19:19
      #define CM_INTEN_OCDONE_SET                                0x00080000
      #define CM_INTEN_OCDONE_CLR                                0xfff7ffff
      #define CM_INTEN_OCDONE_MSB                                19
      #define CM_INTEN_OCDONE_LSB                                19
      #define CM_INTEN_A2WDONE_BITS                              18:18
      #define CM_INTEN_A2WDONE_SET                               0x00040000
      #define CM_INTEN_A2WDONE_CLR                               0xfffbffff
      #define CM_INTEN_A2WDONE_MSB                               18
      #define CM_INTEN_A2WDONE_LSB                               18
      #define CM_INTEN_WRFAIL_BITS                               17:17
      #define CM_INTEN_WRFAIL_SET                                0x00020000
      #define CM_INTEN_WRFAIL_CLR                                0xfffdffff
      #define CM_INTEN_WRFAIL_MSB                                17
      #define CM_INTEN_WRFAIL_LSB                                17
      #define CM_INTEN_BADPASS_BITS                              16:16
      #define CM_INTEN_BADPASS_SET                               0x00010000
      #define CM_INTEN_BADPASS_CLR                               0xfffeffff
      #define CM_INTEN_BADPASS_MSB                               16
      #define CM_INTEN_BADPASS_LSB                               16
      #define CM_INTEN_FLOSSH_BITS                               15:15
      #define CM_INTEN_FLOSSH_SET                                0x00008000
      #define CM_INTEN_FLOSSH_CLR                                0xffff7fff
      #define CM_INTEN_FLOSSH_MSB                                15
      #define CM_INTEN_FLOSSH_LSB                                15
      #define CM_INTEN_FLOSSD_BITS                               14:14
      #define CM_INTEN_FLOSSD_SET                                0x00004000
      #define CM_INTEN_FLOSSD_CLR                                0xffffbfff
      #define CM_INTEN_FLOSSD_MSB                                14
      #define CM_INTEN_FLOSSD_LSB                                14
      #define CM_INTEN_FLOSSA_BITS                               13:13
      #define CM_INTEN_FLOSSA_SET                                0x00002000
      #define CM_INTEN_FLOSSA_CLR                                0xffffdfff
      #define CM_INTEN_FLOSSA_MSB                                13
      #define CM_INTEN_FLOSSA_LSB                                13
      #define CM_INTEN_FLOSSC_BITS                               12:12
      #define CM_INTEN_FLOSSC_SET                                0x00001000
      #define CM_INTEN_FLOSSC_CLR                                0xffffefff
      #define CM_INTEN_FLOSSC_MSB                                12
      #define CM_INTEN_FLOSSC_LSB                                12
      #define CM_INTEN_FGAINH_BITS                               11:11
      #define CM_INTEN_FGAINH_SET                                0x00000800
      #define CM_INTEN_FGAINH_CLR                                0xfffff7ff
      #define CM_INTEN_FGAINH_MSB                                11
      #define CM_INTEN_FGAINH_LSB                                11
      #define CM_INTEN_FGAIND_BITS                               10:10
      #define CM_INTEN_FGAIND_SET                                0x00000400
      #define CM_INTEN_FGAIND_CLR                                0xfffffbff
      #define CM_INTEN_FGAIND_MSB                                10
      #define CM_INTEN_FGAIND_LSB                                10
      #define CM_INTEN_FGAINA_BITS                               9:9
      #define CM_INTEN_FGAINA_SET                                0x00000200
      #define CM_INTEN_FGAINA_CLR                                0xfffffdff
      #define CM_INTEN_FGAINA_MSB                                9
      #define CM_INTEN_FGAINA_LSB                                9
      #define CM_INTEN_FGAINC_BITS                               8:8
      #define CM_INTEN_FGAINC_SET                                0x00000100
      #define CM_INTEN_FGAINC_CLR                                0xfffffeff
      #define CM_INTEN_FGAINC_MSB                                8
      #define CM_INTEN_FGAINC_LSB                                8
      #define CM_INTEN_LOSSH_BITS                                7:7
      #define CM_INTEN_LOSSH_SET                                 0x00000080
      #define CM_INTEN_LOSSH_CLR                                 0xffffff7f
      #define CM_INTEN_LOSSH_MSB                                 7
      #define CM_INTEN_LOSSH_LSB                                 7
      #define CM_INTEN_LOSSD_BITS                                6:6
      #define CM_INTEN_LOSSD_SET                                 0x00000040
      #define CM_INTEN_LOSSD_CLR                                 0xffffffbf
      #define CM_INTEN_LOSSD_MSB                                 6
      #define CM_INTEN_LOSSD_LSB                                 6
      #define CM_INTEN_LOSSA_BITS                                5:5
      #define CM_INTEN_LOSSA_SET                                 0x00000020
      #define CM_INTEN_LOSSA_CLR                                 0xffffffdf
      #define CM_INTEN_LOSSA_MSB                                 5
      #define CM_INTEN_LOSSA_LSB                                 5
      #define CM_INTEN_LOSSC_BITS                                4:4
      #define CM_INTEN_LOSSC_SET                                 0x00000010
      #define CM_INTEN_LOSSC_CLR                                 0xffffffef
      #define CM_INTEN_LOSSC_MSB                                 4
      #define CM_INTEN_LOSSC_LSB                                 4
      #define CM_INTEN_GAINH_BITS                                3:3
      #define CM_INTEN_GAINH_SET                                 0x00000008
      #define CM_INTEN_GAINH_CLR                                 0xfffffff7
      #define CM_INTEN_GAINH_MSB                                 3
      #define CM_INTEN_GAINH_LSB                                 3
      #define CM_INTEN_GAIND_BITS                                2:2
      #define CM_INTEN_GAIND_SET                                 0x00000004
      #define CM_INTEN_GAIND_CLR                                 0xfffffffb
      #define CM_INTEN_GAIND_MSB                                 2
      #define CM_INTEN_GAIND_LSB                                 2
      #define CM_INTEN_GAINA_BITS                                1:1
      #define CM_INTEN_GAINA_SET                                 0x00000002
      #define CM_INTEN_GAINA_CLR                                 0xfffffffd
      #define CM_INTEN_GAINA_MSB                                 1
      #define CM_INTEN_GAINA_LSB                                 1
      #define CM_INTEN_GAINC_BITS                                0:0
      #define CM_INTEN_GAINC_SET                                 0x00000001
      #define CM_INTEN_GAINC_CLR                                 0xfffffffe
      #define CM_INTEN_GAINC_MSB                                 0
      #define CM_INTEN_GAINC_LSB                                 0
#define CM_DSI0HSCK                                              HW_REGISTER_RW( 0x7e101120 ) 
   #define CM_DSI0HSCK_MASK                                      0x00000001
   #define CM_DSI0HSCK_WIDTH                                     1
   #define CM_DSI0HSCK_RESET                                     0000000000
      #define CM_DSI0HSCK_SELPLLD_BITS                           0:0
      #define CM_DSI0HSCK_SELPLLD_SET                            0x00000001
      #define CM_DSI0HSCK_SELPLLD_CLR                            0xfffffffe
      #define CM_DSI0HSCK_SELPLLD_MSB                            0
      #define CM_DSI0HSCK_SELPLLD_LSB                            0
#define CM_CKSM                                                  HW_REGISTER_RW( 0x7e101124 ) 
   #define CM_CKSM_MASK                                          0x003fffff
   #define CM_CKSM_WIDTH                                         22
   #define CM_CKSM_RESET                                         0000000000
      #define CM_CKSM_STEP_BITS                                  21:21
      #define CM_CKSM_STEP_SET                                   0x00200000
      #define CM_CKSM_STEP_CLR                                   0xffdfffff
      #define CM_CKSM_STEP_MSB                                   21
      #define CM_CKSM_STEP_LSB                                   21
      #define CM_CKSM_AUTO_BITS                                  20:20
      #define CM_CKSM_AUTO_SET                                   0x00100000
      #define CM_CKSM_AUTO_CLR                                   0xffefffff
      #define CM_CKSM_AUTO_MSB                                   20
      #define CM_CKSM_AUTO_LSB                                   20
      #define CM_CKSM_OSC_BITS                                   19:18
      #define CM_CKSM_OSC_SET                                    0x000c0000
      #define CM_CKSM_OSC_CLR                                    0xfff3ffff
      #define CM_CKSM_OSC_MSB                                    19
      #define CM_CKSM_OSC_LSB                                    18
      #define CM_CKSM_CFG_BITS                                   17:16
      #define CM_CKSM_CFG_SET                                    0x00030000
      #define CM_CKSM_CFG_CLR                                    0xfffcffff
      #define CM_CKSM_CFG_MSB                                    17
      #define CM_CKSM_CFG_LSB                                    16
      #define CM_CKSM_FRCE_BITS                                  15:8
      #define CM_CKSM_FRCE_SET                                   0x0000ff00
      #define CM_CKSM_FRCE_CLR                                   0xffff00ff
      #define CM_CKSM_FRCE_MSB                                   15
      #define CM_CKSM_FRCE_LSB                                   8
      #define CM_CKSM_STATE_BITS                                 7:0
      #define CM_CKSM_STATE_SET                                  0x000000ff
      #define CM_CKSM_STATE_CLR                                  0xffffff00
      #define CM_CKSM_STATE_MSB                                  7
      #define CM_CKSM_STATE_LSB                                  0

#endif
